參數(shù)資料
型號(hào): PTN3500D
廠商: NXP SEMICONDUCTORS
元件分類: 存儲(chǔ)器
英文描述: Maintenance and control device
中文描述: SPECIALTY MEMORY CIRCUIT, PDSO16
封裝: PLASTIC, SO-16
文件頁數(shù): 10/15頁
文件大?。?/td> 115K
代理商: PTN3500D
Philips Semiconductors
Product specification
PTN3500
Maintenance and control device
2001 Jan 17
10
I
2
C-BUS TIMING CHARACTERISTICS
SYMBOL
I
2
C-bus timing
(see Figure 17; Note 1)
PARAMETER
MIN.
TYP.
MAX.
UNIT
f
SCL
t
SW
t
BUF
t
SU;STA
t
HD;STA
t
r
t
f
t
SU;DAT
t
HD;DAT
t
VD;DAT
t
SU;STO
NOTE:
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
IL
and V
IH
with an input
voltage swing of V
SS
to V
DD
.
SCL clock frequency
400
kHz
tolerable spike width on bus
50
ns
μ
s
μ
s
μ
s
μ
s
μ
s
ns
bus free time
1.3
START condition set–up time
0.6
START condition hold time
0.6
SCL and SDA rise time
0.3
SCL and SDA fall time
0.3
data set–up time
250
data hold time
0
ns
μ
s
μ
s
SCL LOW to data out valid
1.0
STOP condition set–up time
0.6
handbook, full pagewidth
SCL
SDA
MBD820
BIT 0
LSB
(R/W)
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tSU;STO
tf
r
t
tBUF
tSU;STA
1 / fSCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
SW00561
PROTOCOL
Figure 17.
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