參數(shù)資料
型號: PTN1111BD
廠商: NXP SEMICONDUCTORS
元件分類: 時鐘及定時
英文描述: 1:10 PECL clock distribution device
中文描述: LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-358-1, LQFP-32
文件頁數(shù): 2/5頁
文件大?。?/td> 53K
代理商: PTN1111BD
Philips Semiconductors
Product data
PTN1111
1:10 PECL clock distribution device
2
2001 Jun 19
853-2262 26560
FEATURES
80 ps part-to-part skew
20 ps output-to-output skew
Differential design
PECL inputs and outputs
V
BB
reference output voltage available
75 k
input pulldown resistors
Low voltage V
CC
range of 2.375 V to +3.8 V
High signaling rate capability (above 1 GHz)
Pin and function compatible to MC100EP111, MC100LVEP111
Available in LQFP32 package
DESCRIPTION
The PTN1111 is a low-skew, 1:10 PECL clock distribution device.
One selected clock signal out of two selectable inputs is fanned out
to 10 identical, precision time-aligned differential outputs.
The PTN1111 is provided with a V
BB
reference voltage to allow for
single-ended PECL input and with complementary clock inputs to
allow for differential PECL input.
The main purpose and benefit of the PTN1111 is low skew: between
individual outputs of a single PTN1111 (within-part skew or
output-to-output skew) as well as measured from part-to-part.
Within-part skew is realized by careful attention to internal layout
and design of the PTN1111, whereas part-to-part skew is achieved
by control and monitoring of relevant process parameters.
The PTN1111 can be used for high-performance, high-speed clock
distribution in systems which utilize PECL as the primary signaling
standard. Designers can take advantage of the device’s performance
to distribute clocks across a board or backplane, at an extremely high
degree of time alignment, thereby affording system processors to
achieve maximum utilization of the clock cycle.
PIN CONFIGURATION
ST00011
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
PTN1111
V
CC
CLK_SEL
CLK0
V
BB
CLK1
V
EE
V
C
V
C
Q
Q
Q
Q
Q
Q
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q
Q
Q
Q
Q
Q
V
C
V
C
CLK0
CLK1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
V
CC
Power supply voltage
2
CLK_SEL
Clock select input
3, 4
CLK0, CLK0
Differential PECL clock input pair
5
V
BB
Voltage reference output
6, 7
CLK1, CLK1
Differential PECL clock input pair
8
V
EE
V
CCO
Ground
9, 16, 25, 32
Output driver power supply
voltages
Differential PECL output pairs
10–15, 17–24,
26–31
Q0:9, Q0:9
LOGIC DIAGRAM
ST00012
CLK0
CLK0
CLK1
CLK1
CLK_SEL
V
BB
0
1
10
Q0:9
Q0:9
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
PTN1111BD
LQFP32
Plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
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