PT0141(06/03)

Ver:0

8

Preliminary Data Sheet

PT8R2401MD 2.4GHz RF Module

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Power-Down Sequence

The lowest operation power state of PT8R2401 is

Sleep state

, where all clocks including RF and baseband and circuits in the

PT8R2401 is placed in their minimum power mode. In this mode, the control register can be accessed through serial interface

logic and retain their programmed value. To enter into

Sleep state

, power-down command which sets power-down of clock

generator including crystal buffer should be programmed through the serial interface. After power-down command, the

DATACLK from the PT8R2401 will stop until it comes back to

Idle state

. To escape from

Sleep state

, power-up command

which sets power-up of clock generator should be programmed through the serial interface. After power-up command, the

DATACLK will start again from the PT8R2401 into external baseband.

Figure 7. Power-down sequence procedure timing-diagram

Idle

Sleep

JTAG

Programming

TXACTIVE

TXDATA_EN

TXDATA

RXACTIVE

SYNCDETECT

RXDATA

DATACLK

HOP CMD

RESET

POWER

VCO Tuning

Transmit Operation

Power Down CMD

Tx-Ramp-Up

Idle

Power Up CMD