PT0141(06/03)

Ver:0

10

Preliminary Data Sheet

PT8R2401MD 2.4GHz RF Module

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Serial Programming Interface (JTAG interface)

The serial programming interface is a JTAG boundary-scan architecture compliant with IEEE 1149.1. Interconnection between

the serial interface and external baseband consists of four 1-bit digital signals : control data input(TDI), control mode select

(TMS), control clock (TCK) and control data output (TDO). You must refer to the full IEE std 1149.1-1990 Standard Test

Access Port and Boundary-Scan Architecture document for a complete, definitive description of the operation of the

fundamentals of the JTAG interface. PT1002 support TCK up to 16MHz.

Table 1. TAP instructions

Instruction

EXTEST

Opcode

0x000000

Description

EXTEST initiates testing of external circuitry, typically board-level interconnects and off chip

circuitry. EXTEST connects the Boundary-Scan register between TDI and TDO in the SHIFT_DR

state only. When EXTEXT is selected, all output signal pin values are driven by values shifted into

the Boundary-Scan register and may change only on the falling-edge of TCK in the Update_DR

state. Also, when EXTEST is selected, all system input pin states must be loaded into the

Boundary-Scan register on the rising-edge of TCK in the Capture_DR state. Values shifted into

input latches in the Boundary-Scan register are never used by the processor’s internal logic.

SAMPLE /

PRELOAD

0x000001

SAMPLE / PRELOAD performs two functions:

When the TAP controller is in the Capture-DR state, the SAMPLE instruction occurs on the rising

edge of TCK and provides a snapshot of the component’s normal operation without interfering with

that normal operation. The instruction causes Boundary-Scan register cells associated with outputs

to SAMPLE the value being driven by or to the processor.

When the TAP controller is in the Update-DR state, the PRELOAD instruction occurs on the

falling edge of TCK. This instruction causes the transfer of data held in the Boundary-Scan cells to

the slave register cells. Typically the slave-latched data is then applied to the system outputs by

means of the EXTEST instruction.

IDCODE

0x011111

IDCODE is used in conjunction with the device identification register. It connects the identification

register between TDI and TDO in the Shift_DR state. When selected, IDCODE parallel-loads the

hard-wired identification code (32 bits) on TDO into the identification register on the rising edge of

TCK in the Capture_DR state.

NOTE: The device identification register is not altered by data being shifted in on TDI.

REGISTER

PROGRAMMING

0x1SSSSS

REGISTER PROGRAMMING instruction select the REGISTER with address indicator SSSSS.

When the TAP controller is in the Capture-DR state, the REGISTER PROGRAMMING

instruction occurs on the rising edge of TCK and executes a snapshot of register addressed SSSSS

into serial register.

When the TAP controller is in the Update-DR state, the REGISTER PROGRAMMING

instruction occurs on the falling edge of TCK. This instruction causes the transfer of data held in

serial register to register addressed SSSSS.

BYPASS

0x111111

BYPASS instruction selects the Bypass register between TDI and TDO pins while in SHIFT_DR

state, effectively bypassing the processor’s test logic. 0 is captured in the CAPTURE_DR state.

While this instruction is in effect, all other test data registers have no effect on the operation of the

system. Test data registers with both test and system functionality perform their system functions

when this instruction is selected.