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參數(shù)資料
| 型號： | PT7A4410L |
| 英文描述： | Incremental Encoder Interface Accelerator Verilog Module |
| 中文描述： | T1/E1/OC3系統(tǒng)同步？ |
| 文件頁數(shù)： | 34/34頁 |
| 文件大?。?/td> | 306K |
| 代理商： | PT7A4410L |
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Data Sheet
PT7A4402B/4402L
T1/E1 System Synchronizer
PT0100(08/02)
Ver:0
9
Output Interface Circuit
The Output Interface Circuit consists of the Tapped Delay Lines
and E1/T1 Dividers as shown in Figure 5.
Signals from the DCO are sent to Tapped Delay Lines to gener-
ate two clock signals, 16.384MHz and 12.352MHz, which are
divided in the T1 and E1 Dividers respectively to provide
needed clock and frame signals.
The T1 Divider uses the 12.352MHz signal to generate two
clock signals, C1.5 and C3. They have a nominal 50% duty
cycle.
The E1 Divider uses the 16.384MHz signal to generate four
clock signals and three frame signals, i.e., C2, C4, C8, C16,
F0, F8 and F16. The frame signals are generated directly from
the C16 signal.
The C2, C4, C16 and C8 signals have nominal 50% duty cycle.
All the frame and clock outputs are locked to each other for all
operating states. They have limited driving capability and
should be buffered when driving high capacitance loads.
Figure 4. Block Diagram of DPLL
Signal
From
DCO2
Tapped
Delay
Line
T1
Divider
Signal
From
DCO1
Tapped
Delay
Line
E1
Divider
12MHz
16MHz
C1.5
C3
C2
C4
C8
C16
F0
F8
F16
Figure 5. Block Diagram of Output Interface Circuit
Control Circuit
Phase
Detector
Limiter
Loop
Filter
Virtual
Reference
from TIE
Corrector
Feedback Signal
From
Frequency Select MUX
State Select From
Input Impairment
Monitor
State Select
From
State Machine
DPLL Reference
to
Output Interface
Circuit
DCO
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