參數(shù)資料
型號(hào)： PT7A4409
英文描述： Single Axis Bundled System Accelerator1 System Manual
中文描述： T1/E1/0C3系統(tǒng)同步？
文件頁(yè)數(shù)： 8/34頁(yè)
文件大?。?/td> 306K
代理商： PT7A4409
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Data Sheet
PT7A4402B/4402L
T1/E1 System Synchronizer
PT0100(08/02)
Ver:0
16
Reset Circuit
A simple power up reset circuit with about a 50
s reset active
(low) time is shown in Figure 13. Resistor R
P is for protection
only. The reset low time is not critical but should be greater
than 300ns.
Figure 13. Power-up Reset Circuit
Power Supply Decoupling
The PT7A4402B/4402L has two V
CC pins and two GND pins.
Power decoupling capacitors should be included as shown in
Figure 14.
Figure 14. Power Supply Decoupling
+
1
5
15
18
C1
0.1
F
C2
0.1
F
PT7A4402B
/4402L
+
Detailed Specifications
Definitions of Critical Performance
Specifications
Intrinsic Jitter: Intrinsic jitter is the jitter produced by the
synchronizing circuit. It is measured by applying a reference
signal with no jitter to the input of the device, and measuring
its output jitter. Intrinsic jitter may also be measured when the
device is in a non-synchronizing mode - such as free running
or holdover - by measuring the output jitter of the device.
Intrinsic jitter is usually measured with various band limiting
filters depending on the applicable standards.
Jitter Tolerance: Jitter tolerance is a measure of the ability of
a PLL to operate properly (i.e., remain in lock and/or regain
lock in the presence of large jitter magnitudes at various jitter
frequencies) when jitter is present on its reference. The appli-
cable standard specifies how much jitter to apply to the refer-
ence when testing for jitter tolerance.
Jitter Transfer: Jitter transfer or jitter attenuation refers to the
magnitude of jitter at the output of a device with respect to a
given amount of jitter at the input of the device. Input jitter is
applied at various amplitudes and frequencies, and output jit-
ter is measured with various filters depending on the appli-
cable standards.
Its 3 possible input frequencies and 9 outputs give the
PT7A4402B/4402L 27 possible jitter transfer combinations.
However, only three cases of the jitter transfer specifications
are given in the AC Electrical Characteristics; as the remaining
combinations can be derived from them.
For the PT7A4402B/4402L, two internal elements determine
the jitter attenuation. They are internal 1.9Hz low pass loop
filter and phase slope limiter. The phase slope limiter limits
the output phase slope to 5ns/125
s. Therefore, if the input
signal exceeds this rate, such as for very large amplitude low
frequency input jitter, the maximum output phase slope will
be limited (i.e., attenuated) to 5ns/125
s.
It should be noted that 1UI at 1.544MHz (644ns) is not equal
to 1UI at 2.048MHz (488ns). A transfer value using different
input and output frequencies must be calculated in common
units (e.g., seconds) as shown in the following example.
Example : When the T1 input jitter is 20UI (T1 UI Units) and
the T1 to T1 jitter attenuation is 18dB, The T1 and E1 output
jitter can be calculated as follows:
PT7A4402B/4402L
RST
+5V
R
10k
R
P
1k
C
10nF
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