參數(shù)資料
型號: PSD853F2-15JIT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 93/103頁
文件大?。?/td> 1180K
代理商: PSD853F2-15JIT
9/103
PSD8XXF2/3/4/5
KEY FEATURES
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A simple interface to 8-bit microcontrollers that
use either multiplexed or non-multiplexed
busses. The bus interface logic uses the control
signals generated by the microcontroller
automatically when the address is decoded and
a READ or WRITE is performed. A partial list of
the MCU families supported include:
– Intel 8031, 80196, 80186, 80C251, and
80386EX
– Motorola 68HC11, 68HC16, 68HC12, and
683XX
– Philips 8031 and 8051XA
– Zilog Z80 and Z8
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Internal 1 or 2 Mbit Flash memory. This is the
main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with
user-specified addresses.
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Internal secondary 256 Kbit Flash boot memory.
It is divided into four equal-sized blocks that can
be accessed with user-specified addresses.
This secondary memory brings the ability to
execute code and update the main Flash
concurrently.
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Optional 16, 64 or 256 Kbit SRAM. The SRAM’s
contents can be protected from a power failure
by connecting an external battery.
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CPLD with 16 Output Micro Cells (OMCs) and
24 Input Micro Cells (IMCs). The CPLD may be
used to efficiently implement a variety of logic
functions for internal and external control.
Examples include state machines, loadable
shift registers, and loadable counters.
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Decode PLD (DPLD) that decodes address for
selection of internal memory blocks.
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27 individually configurable I/O port pins that
can be used for the following functions:
– MCU I/Os
–PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as
open-drain outputs.
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Standby current as low as 50 A for 5 V devices.
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Built-in JTAG compliant serial port allows full-
chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.
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Internal page register that can be used to
expand the microcontroller address space by a
factor of 256.
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Internal programmable Power Management
Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can
automatically detect a lack of microcontroller
activity and put the PSD8XXF into Power-down
mode.
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Erase/WRITE cycles:
– Flash memory – 100,000 minimum
– PLD – 1,000 minimum
– Data Retention: 15 year minimum (for Main
Flash memory, Boot, PLD and Configuration
bits)
相關PDF資料
PDF描述
PSD833F2-15M 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
PSD835G2V-B-90MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-B-90U Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-B-90UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-C-12B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
相關代理商/技術參數(shù)
參數(shù)描述
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