參數(shù)資料
型號： PSD835F1V-12B81
廠商： 意法半導體
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù)： 76/110頁
文件大小： 570K
代理商： PSD835F1V-12B81
PSD835G2
PSD8XX Family
67
The
PSD835G2
Functional
Blocks
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
PLD
**
PLD
**
PLD
**
*
PLD
array
DBE
ALE
CNTL2
CNTL1
CNTL0
Addr.
1 = off
PMMR2
Bit 0 0 = Address A[7:0] inputs to the PLD AND array are connected.
1 = Address A[7:0] inputs to the PLD AND array are disconnected, saving power.
Note: In 80C51 mode, A[7:1] comes from Port F (PF1-PF3) and AD10 [3:0].
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to PLD AND array is disconnected, saving power.
Bit 5 0 = ALE input to the PLD AND array is connected.
1 = ALE input to PLD AND array is disconnected, saving power.
Bit 6 0 = DBE input to the PLD AND array is connected.
1 = DBE input to PLD AND array is disconnected, saving power.
**Unused bits should be set to 0.
**Refer to Table 14 the signals that are blocked on pins CNTL0-2.
Bit 1 0 = Automatic Power Down (APD) is disabled.
1 = Automatic Power Down (APD) is enabled.
Bit 3 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
Bit 5 0 = CLKIN input to the PLD Micro
Cells is connected.
1 = CLKIN input to PLD Micro
Cells is disconnected, saving power.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
**
PLD
*
APD
*
Mcell clk
Array clk
Turbo
Enable
1 = off
1 = on
Table 27. Power Management Mode Registers (PMMR0, PMMR2)**
PMMR0
***Bits 0, 2, 6, and 7 are not used, and should be set to 0.
***The PMMR0, and PMMR2 register bits are cleared to zero following power up.
***Subsequent reset pulses will not clear the registers.
相關(guān)PDF資料
PDF描述
PSD835F1V-12B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-12J CONN RECEPT 26POS 2MM IDT GOLD
PSD835F1V-12JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-12M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F2V-12B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
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PSD835G2V-90U 功能描述:靜態(tài)隨機存取存儲器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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