參數(shù)資料
型號(hào)： PSD835F1V-12B81
廠商： 意法半導(dǎo)體
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
文件頁數(shù)： 15/110頁
文件大?。?/td> 570K
代理商： PSD835F1V-12B81
PSD835G2
PSD8XX Family
11
Table 6 shows the offset addresses to the PSD835G2 registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD835G2 registers. Table 6 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
7.0 PSD835G2
Register
Description and
Address Offset
Register Name
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Other*
Description
Data In
00
01
10
11
30
40
41
Reads Port pin as input,
MCU I/O input mode
Control
32
42
43
Selects mode between
MCU I/O or Address Out
Stores data for output
Data Out
04
05
14
15
34
44
45
to Port pins, MCU I/O
output mode
Direction
06
07
16
17
36
46
47
Configures Port pin as
input or output
Configures Port pins as
either CMOS or Open
Drive Select
08
09
18
19
38
48
49
Drain on some pins, while
selecting high slew rate
on other pins.
Input Micro
Cell
0A
0B
1A
Reads Input Micro
Cells
Reads the status of the
Enable Out
0C
0D
1C
4C
output enable to the I/O
Port driver
Read – reads output of
Output
Micro
Cells A
Micro
Cells A
20
Write – loads Micro
cell
Flip-Flops
Read – reads output of
Output
Micro
Cells B
Micro
Cells B
21
Write – loads Micro
cell
Flip-Flops
Mask
22
Blocks writing to the
Micro
Cells A
Output Micro
Cells A
Mask
23
Blocks writing to the
Micro
Cells B
Output Micro
Cells B
Flash Protection
C0
Read only – Flash Sector
Protection
Flash Boot
Read only – PSD Security
Protection
C2
and Flash Boot Sector
Protection
JTAG Enable
C7
Enables JTAG Port
PMMR0
B0
Power Management
Register 0
PMMR2
B4
Power Management
Register 2
Page
E0
Page Register
Places PSD memory
VM
E2
areas in Program and/or
Data space on an
individual basis.
Memory_ID0
F0
Read only – Flash and
SRAM size
Memory_ID1
F1
Read only – Boot type
and size
Table 6. Register Address Offset
相關(guān)PDF資料
PDF描述
PSD835F1V-12B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-12J CONN RECEPT 26POS 2MM IDT GOLD
PSD835F1V-12JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F1V-12M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F2V-12B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD835G2-70U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2-90U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2-90UI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2V-12UI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2V-90U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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