參數(shù)資料
型號(hào)： PSD834F2
英文描述： Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍)
中文描述： Flash在系統(tǒng)可編程（ISP）為周邊8位微控制器（用于8位微控制器的閃速的ISP外圍）
文件頁(yè)數(shù)： 62/98頁(yè)
文件大?。?/td> 595K
代理商： PSD834F2
PSD8XXF2/3/4/5
62/98
TSTAT behaves the same as Ready/Busy de-
scribed inthe sectionentitled “Ready/Busy (PC3)”,
on page 15. TSTAT is High when the PSD8xxF2/
3/4/5 device is in Read mode (primary and sec-
ondary Flash memory contents can be read).
TSTAT is Low when Flash memory Program or
Erase cycles are in progress, and also when data
is being written to the secondary Flash memory.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com-
mand. This facilitates a wired-OR connection of
TSTAT signals from multiple PSD8xxF2/3/4/5 de-
vices anda wired-OR connection of TERR signals
from those same devices. Thisis useful when sev-
eral PSD8xxF2/3/4/5 devices are “chained” to-
gether in a JTAG environment.
Security and Flash memory Protection
When the security bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port,only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Security Bit can be
set in PSDsoft Express Configuration.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The sector protect bits can be set in PSD-
soft Express Configuration.
INITIAL DELIVERY STATE
When delivered from ST, the PSD8xxF2/3/4/5 de-
vice has all bits in the memory and PLDs set to 1.
The PSD8xxF2/3/4/5 Configuration Register bits
are set to 0. The code, configuration, and PLD log-
ic are loaded using the programming procedure.
Information for programming the device is avail-
able directly from ST. Please contact your local
sales representative.
Table 35. JTAG Enable Register
Note: 1. The state of Reset (Reset) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configu-
ration bit (via PSDsoft Express). However, Reset (Reset) prevents or interrupts JTAG operations if the JTAG enable register is used
to enable the JTAG signals.
Bit 0
JTAG_Enable
0 = off JTAGport is disabled.
1 = on JTAGport is enabled.
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
X
0
Not used, and should be set to zero.
Bit 3
X
0
Not used, and should be set to zero.
Bit 4
X
0
Not used, and should be set to zero.
Bit 5
X
0
Not used, and should be set to zero.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
相關(guān)PDF資料
PDF描述
PSD835G2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲(chǔ)器可編程外設(shè))
PSD835G2 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-254AA Tabless package; Similar to IRHMJ57160 with optional Total Dose Rating of 1000kRads
PSD835G2V 150V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package. Also available with 300 kRads Total Dose Rating.; Similar to IRHNA67164 with optional Total Dose Rating of 300 kRads.
PSD835G2-B-12B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F2-B-12B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
PSD834F2-70J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-70M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD834F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2-90JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*