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參數(shù)資料
| 型號(hào)： | PSD813F5V |
| 英文描述： | -60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA9064 with optional Total Dose Rating of 300kRads |
| 中文描述： | Flash在系統(tǒng)編程（ISP）外設(shè)的8位微控制器 |
| 文件頁(yè)數(shù)： | 33/103頁(yè) |
| 文件大?。?/td> | 1185K |
| 代理商： | PSD813F5V |
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PSD81XFX, PSD83XF2, PSD85XF2
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate three External Chip Se-
lect (ECS0-ECS2), routed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these three External Chip Select (ECS0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in Figure 11, the CPLD has the following
blocks:
I
24 Input Macrocells (IMC)
I
16 Output Macrocells (OMC)
I
Macrocell Allocator
I
Product Term Allocator
I
AND Array capable of generating up to 137
product terms
I
Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD8XXFX internal
data bus and can be directly accessed by the
MCU. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 13. Macrocell and I/O Port
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
M
M
M
M
D
D
Q
Q
Q
G
D
Q D
WR
WR
PDR
DATA
PALLOCATOR
DIR
SELECT
INPUT
PFROM OTHER
MACROCELLS
POLARITY
PROUP TO 10
CLOCK
PR
DI LD
D/T
CK
CL
Q
SELECT
PT CLEAR
PT
GLOBAL
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET
MCU DATA IN
/REG
SELECT
MACTO
IALLOC.
OCPLD
TO OTHER I/O PORTS
P
P
MCU ADDRESS / DATA BUS
MOUT TO
MCU
CDATA
A
CPLD OUTPUT
I/O PIN
AI02874
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD813F5VA-15J | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 3.0V 1M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD813F5VA-15U | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD813F2VA-15U RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD813FH-15J | 制造商:WSI 功能描述: |
| PSD813FH-90J | 制造商:WSI 功能描述: |
| PSD813FN-15J | 制造商:WSI 功能描述: |
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