參數(shù)資料
型號： PSD813F2A-15JI
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 72/110頁
文件大?。?/td> 837K
代理商： PSD813F2A-15JI
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
64/110
For Users of the HC11 (or compatible)
The HC11 turns off its E clock when it sleeps.
Therefore, if you are using an HC11 (or compati-
ble) in your design, and you wish to use the Pow-
er-down mode, you must not connect the E clock
to CLKIN (PD1). You should instead connect a
crystal oscillator to CLKIN (PD1). The crystal oscil-
lator frequency must be less than 15 times the fre-
quency of AS. The reason for this is that if the
frequency is greater than 15 times the frequency
of AS, the PSD keeps going into Power-down
mode.
Other Power Saving Options
The PSD offers other reduced power saving op-
tions that are independent of the Power-down
mode. Except for the SRAM Stand-by and PSD
Chip Select Input (CSI, PD2) features, they are en-
abled by setting bits in PMMR0 and PMMR2.
Figure 33. Enable Power-down Flow Chart
PLD Power Management
The power and speed of the PLDs are controlled
by the Turbo Bit (Bit 3) in PMMR0. By setting the
bit to '1,' the Turbo mode is off and the PLDs con-
sume the specified stand-by current when the in-
puts are not switching for an extended time of
70ns. The propagation delay time is increased by
10ns after the Turbo Bit is set to '1' (turned off)
when the inputs change at a composite frequency
of less than 15 MHz. When the Turbo Bit is reset
to '0' (turned on), the PLDs run at full power and
speed. The Turbo Bit affects the PLD’s DC power,
AC power, and propagation delay.
Blocking MCU control signals with the bits of
PMMR2 can further reduce PLD AC power con-
sumption.
SRAM Standby Mode (Battery Backup). The
PSD supports a battery backup mode in which the
contents of the SRAM are retained in the event of
a power loss. The SRAM has Voltage Stand-by
(VSTBY, PC2) that can be connected to an external
battery. When VCC becomes lower than VSTBY
then the PSD automatically connects to Voltage
Stand-by (VSTBY, PC2) as a power source to the
SRAM. The SRAM Standby Current (ISTBY) is typ-
ically 0.5A. The SRAM data retention voltage is
2V minimum. The Battery-on Indicator (VBATON)
can be routed to PC4. This signal indicates when
the VCC has dropped below VSTBY.
Enable APD
Set PMMR0 Bit 1 = 1
PSD in Power
Down Mode
ALE/AS idle
for 15 CLKIN
clocks?
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
AI02892
相關PDF資料
PDF描述
PSD834F2VA-15MI 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
PSD854F2A-90MT 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
PSD854F2A-90UT 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
PSH665-FREQ-OUT1 VCXO, SINE OUTPUT, 465 MHz - 865 MHz
PSM3-022K 1 ELEMENT, 0.022 uH, GENERAL PURPOSE INDUCTOR, SMD
相關代理商/技術參數(shù)
參數(shù)描述
PSD813F2A-15JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F2A-15JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F2A-15M 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F2A-15MI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F2A-15MIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*