參數(shù)資料
型號(hào)： PSD712S5
英文描述： Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個(gè)可編程輸入/輸出，通用PLD的有66個(gè)輸入）
文件頁(yè)數(shù)： 56/104頁(yè)
文件大小： 515K
代理商： PSD712S5
PSD7XX Family
13-56
The PSD7XX has internal EPROM and SRAM memory blocks. The memory select signals
come from the DPLD and are user-defined in the PSDsoft Software.
EPROM
The PSD7XX provides three EPROM densities: 256K bit, 512K bit or 1M bit. The EPROM
is divided into eight blocks. The EPROM can be configured as 32K x 8, 64K x 8 or
128K x 8 for eight-bit data busses and 16K x 16, 32K x 16 or 64K x 16 for 16-bit data buses.
Each block has its own EPROM select. Blocks zero to six have one select (ES0-ES6) and
block 7 has two selects, ES7A and ES7B, either of which enables Block 7. The dual selects
allow Block 7 to reside in two separate memory spaces.
A typical application would be to store an MCU reset vector residing in the memory space
and accessed by ES7B. The rest of the Block 7 memory space would be accessed by
ES7A. The same technique can also be used to store the Configuration bytes of the Intel
80251 microcontroller which reside at the high end of the memory space.
SRAM
The SRAM has 4K bits of memory that can be configured as 512 x 8 or 256 x 16. The
SRAM is enabled from the RS0 output of the DPLD. The SRAM has a battery back-up
mode which is automatically invoked when the supply voltage drops under the standby
voltage. SRAM write protection is provided in back-up mode.
Memory Select Map
The EPROM and SRAM select are outputs from the DPLD whose equations are defined
using PSDabel. The following rules apply to the memory space definitions:
1. EPROM block select space should not be larger than the physical block size
2. EPROM block select space must not overlap
3. SRAM, I/O and Peripheral I/O spaces cannot overlap
4. SRAM, I/O and Peripheral I/O spaces can overlap EPROM with priority given to the
SRAM or I/O. This allows the SRAM or I/O to utilize the EPROM space that is not used.
Memory Blocks
相關(guān)PDF資料
PDF描述
PSD713S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
PSD813F4 Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM)
PSD813F Flash In-System-Programmable Microcontroller Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM)
PSD813FH(中文) Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場(chǎng)可編程微控制器)
PSD813FN(中文) Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場(chǎng)可編程微控制器)
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