參數(shù)資料
型號: PSD602E1
英文描述: Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞(可編程邏輯,4K的位的SRAM,26我個可編程輸入/輸出,通用PLD的有63個輸入)
文件頁數(shù): 70/84頁
文件大小: 426K
代理商: PSD602E1
PSD6XX Family
11-70
-70
-90
-15
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
t
AVWL
ALE or AS Pulse Width
18
20
28
ns
Address Setup Time
(Note 4)
5
6
10
ns
Address Hold Time
(Note 4)
7
8
11
ns
Address Valid to Leading Edge
of WR
(Notes 4 and 6)
18
20
30
ns
t
SLWL
t
DVWH
t
WHDX
t
WLWH
t
WHAX
CS Valid to Leading Edge or WR
(Note 6)
22
25
35
ns
WR Data Setup Time
(Note 6)
12
15
22
WR Data Hold Time
(Note 6)
5
5
5
ns
WR Pulse Width
(Note 6)
18
20
28
ns
Trailing Edge of WR to
Address Invalid
(Note 6)
0
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 6)
25
30
38
ns
t
WLMV
WR Valid to Port Output Valid
Using Micro
Cell Register Load
(Note 6 and 6a)
25
30
38
ns
t
DVMV
Data Valid to Port Output Valid
Using Micro
Cell Register Data In
(Note 6 and 6b)
25
30
38
ns
In 16-Bit Bus Mode
(Note 5)
20
30
38
ns
t
AVPV
Address Input Valid to
Address Output Delay
In 8-Bit Bus Mode
(Note 5)
22
32
48
ns
Write Timing
Microcontroller Interface – AC/DC Parameters
NOTE:
6.
WR timing has the same timing as E, DS, LDS, UDS, WRL, WRH signals.
6a. Assuming data is stable before active write signal.
6b. Assuming write is active before data becomes valid.
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PDF描述
PSD603E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
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