參數(shù)資料
型號(hào)： PSD501B1-C-70U
廠商： 意法半導(dǎo)體
英文描述： Low Cost Field Programmable Microcontroller Peripherals
中文描述： 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備
文件頁數(shù)： 48/153頁
文件大?。?/td> 1036K
代理商： PSD501B1-C-70U
PSD5XX Famly
45
9.3.11 Port A – Functionality and Structure
Port A is the most flexible of all the I/O ports. It can be configured to perform one or more
of the following functions:
J
Standard MCU I/O Mode
J
PLD I/O
J
Address Out – latched address lines assigned to pins PA[0-7]
J
Address In – input port for other lines, inputs can be latched by ALE.
J
Special Function Out – pins PA0 – PA3 can be configured as dedicated timer outputs.
J
Peripheral I/O
Figure 21 shows the structure of a Port A pin. If the pin is configured as an output port, the
multiplexer selects one of its four inputs as output. If the pin is configured as an input, the
input connects to :
1. Data In Register as input in Standard MCU I/O Mode
or
2. PA Macrocell as PLD input
or
3. PA Macrocell as Address In input (latched for multiplexed bus).
9.3.12 Port B – Functionality and Structure
Port B is similar to Port A in structure. It can be configured to perform one or more of the
following functions:
J
Standard MCU I/O Mode
J
PLD I/O
J
Address Out – address lines A[0-7] for 8-bit multiplexed bus, or address lines
A[8-15] for 16-bit multiplexed bus are assigned to pins PB[0-7].
J
Special Function Out – pins PB0 - PB3 are configured as dedicated Timer outputs.
Figure 22 shows the structure of a Port B pin. If the pin is configured as an output port, the
multiplexer selects one of its four inputs as output. If the pin is configured as input, the input
connects to :
J
Data In Register as input in Standard MCU I/O Mode
or
J
PB Macrocell as PLD input
I/OPorts
(Cont.)
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