參數(shù)資料
型號: PSD413A2
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,40個可編程I/O,通用PLD有59個輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備(可編程邏輯,16K的位的SRAM,40余個可編程輸入/輸出,通用PLD的有59個輸入)
文件頁數(shù): 74/97頁
文件大小: 309K
代理商: PSD413A2
PSD4XX Famly
4-74
Reset Input
The reset input to the PSD4XX (RESET) is an active low signal which resets some of the
internal devices and configuration registers. The Timing Diagram in the AC/DC
characterization section shows the reset signal timing requirement. The active low range
has a minimum T1 duration. After the rising edge of RESET, the PSD4XX remains in
reset during T2 range. (See Figure 47). The PSD4XX must be reset at power up before it
can be used.
ZPLDand Memory During Reset
While the Reset Input is active, the ZPLD generates outputs as defined in the PSDabel
equations. The EPROM and SRAM blocks respond to the microcontroller bus cycle during
reset, but the data is not guaranteed.
Register Values During and After Reset
Table 24 summarizes the status of the volatile register values during and after reset.
The default values of the volatile registers are “0” after reset.
ZPLDMacrocell Initialization
The D flip flops in the macrocells in the GPLD can be cleared by:
J
A product term (.RE) defined by the user in PSDabel, or
J
The MACRO-RST (Reset) input, enabled and defined in PSDabel.
Register Name
Device
Reset State
Control
Port A, B, C, D, E
Set to “0”
(Address Out Mode)
Data Out
(data or address)
Port A, B, C, D, E
Set to “0”
Direction
Port A, B, C, D, E
Set to “0” – Input Mode
Open Drain
Port C, D
Set to “0” – CMOS Outputs
Page Register
Page Logic
Set to “0”
PMMR0, PMMR1
Power Management Unit
Set to “0”
VM
Volatile Memory
Set to “0”
System
Configuration
(Cont.)
Table 24. Registers Reset Values
Port Configuration
Reset
Stand-by Mode
Port I/O
Input
Unchanged
ZPLD Output
Active
Depend on Inputs to the ZPLD
Address Out
Tri-stated
Not Defined
Data Port
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Table 25. I/OPin Status During Reset and Standby Mode
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