參數(shù)資料
型號: PSD413A2
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備(可編程邏輯,16K的位的SRAM,40余個(gè)可編程輸入/輸出,通用PLD的有59個(gè)輸入)
文件頁數(shù): 21/97頁
文件大小: 309K
代理商: PSD413A2
PSD4XX Famly
4-21
The PSD4XXA2
ZPLDBlock
Key Features
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2 Embedded ZPLD devices
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24 macrocells
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Combinatorial/registered outputs
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Maximum 126 product terms
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Programmable output polarity
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User configured register clear/preset
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User configured register clock input
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59 Inputs
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Accessible via 24 I/O pins
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Power Saving Mode
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UV-Erasable
General Description
The ZPLD block has 2 embedded PLD devices:
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DPLD
The Address Decoding PLD, generating select signals to internal I/O or memory blocks.
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GPLD
The General Purpose PLD provides 24 programmable macrocells for general
or complex logic implementation; dedicated to user application.
Figure 10 shows the architecture of the ZPLD. The PLD devices all share the same
input bus. The true or complement of the 59 input signals are fed to the programmable
AND-ARRAY. Names and source of the input signals are shown in Table 4. The PA, PB, PE
signals, depending on user configuration, can either be macrocell feedbacks or inputs from
Port A, B or E.
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