參數(shù)資料
型號： PSD413A2-90J
英文描述： 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-3 package; A IRHNB7260 with Standard Packaging
中文描述： 現(xiàn)場可編程外圍
文件頁數(shù)： 84/123頁
文件大小： 657K
代理商： PSD413A2-90J
PSD4XX Famly
81
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
CC
V
IH
V
IL
V
IH1
V
IL1
V
HYS
Supply Voltage
All Speeds
4.5
5
5.5
V
High Level Input Voltage
4.5 V < V
CC
< 5.5 V
4.5 V < V
CC
< 5.5 V
(Note 1)
2
V
CC
+ 0.5
0.8
V
Low Level Input Voltage
–0.5
V
Reset High Level Input Voltage
0.8 V
CC
–0.5
V
CC
+ 0.5
0.2 V
CC
–0.1
V
Reset Low Level Input Voltage
(Note 1)
V
Reset Pin Hysteresis
0.3
V
V
OL
Output Low Voltage
I
OL
= 20 μA, V
CC
= 4.5 V
0.01
0.1
V
I
OL
= 8 mA, V
CC
= 4.5 V
I
OH
= –20 μA, V
CC
= 4.5 V
0.15
0.45
V
V
OH
Output High Voltage
4.4
4.49
V
I
OH
= –2 mA, V
CC
= 4.5 V
2.4
3.9
V
V
SBY
I
SBY
I
IDLE
V
DF
SRAM Standby Voltage
2.7
V
CC
1
V
SRAM Standby Current
V
CC
= 0 V
V
CC
> V
SBY
Only on V
STBY
0.5
μA
Idle Current (V
STDBY
Pin)
SRAM Data Retention Voltage
–0.1
0.1
μA
2
V
I
SB1
(PSD4XX)
Standby Supply
Current
Power Down Mode
CSI >V
CC
–0.3 V (Note 2)
50
100
μA
Sleep Mode
CSI >V
CC
–0.3 V (Note 3)
30
40
μA
I
SB2
(ZPSD4XX)
Current
Standby Supply
Power Down Mode
CSI >V
CC
–0.3 V (Note 2)
25
50
μA
Sleep Mode
CSI >V
CC
–0.3 V (Note 3)
V
SS
< V
IN
< V
CC
0.45 < V
IN
< V
CC
10
20
μA
I
LI
I
LO
Input Leakage Current
–1
±0.1
1
μA
Output Leakage Current
–10
±5
10
μA
ZPLD_TURBO = OFF,
f = 0 MHz (Note 4)
See I
SB1
and I
SB2
I
CC
(DC)
(Note 4a)
Operating
Supply Current
ZPLD Adder
ZPLD_TURBO = ON,
f = 0 MHz
400
700
μA/PT
EPROM Adder
f = 0 MHz
0
mA
SRAM Adder
f = 0 MHz
0
mA
ZPLD AC Adder
See
Fig. 38
4
mA/MHz
CMiser = ON and
(8-bit bus mode)
EPROM AC Adder
0.8
2
mA/MHz
All other cases
1.8
4
mA/MHz
I
CC
(AC)
(Note 4a)
CMiser = ON and
(8-bit bus mode)
1.4
2.7
mA/MHz
SRAM AC Adder
CMiser = ON and
(16-bit bus mode)
2
4
mA/MHz
CMiser = OFF
3.8
7.5
mA/MHz
13.6 DC Characteristics
(5 V ± 10% Versions)
NOTES:
1.
Reset input has hysteresis. V
IL1
is valid at or below 0.2V
CC
–0.1. V
IH1
is valid at or above 0.8V
CC
.
CSI is high or internal Power Down mode is active.
Sleep mode bit is set and internal Power Down is active.
See ZPLD I
CC
/Frequency Power Consumption graph for details.
4a. I
OUT
= 0 mA.
2.
3.
4.
相關PDF資料
PDF描述
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相關代理商/技術參數(shù)
參數(shù)描述
PSD413A2-C-70L 制造商:WSI 功能描述:
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PSD4235G2-90U 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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