參數(shù)資料
型號: PSD413A2-90J
英文描述: 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-3 package; A IRHNB7260 with Standard Packaging
中文描述: 現(xiàn)場可編程外圍
文件頁數(shù): 78/123頁
文件大小: 657K
代理商: PSD413A2-90J
PSD4XX Famly
75
System
Configuration
(cont.)
Register Name
Register Function
Data In
This Register is used to read the inputs on the port pins.
Control
A
0
sets the corresponding port pin in Address Out Mode.
A
1
sets the pin in MCU I/O Mode.
Data Out
Holds the output data in the MCU I/O Mode.
This register is used to control the data flow in the I/O ports.
A
0
sets the corresponding pin as an input pin.
A
1
sets the pin as an output pin.
Direction
Open Drain
A
0
sets the corresponding pin driver as a CMOS driver.
A
1
sets the pin driver as an Open Drain Driver.
PLD – I/O
A read only status register; a
1
indicates the corresponding pin
is configured as a PLD pin.
Macrocell Out
This register holds the outputs of the GPLD macrocells.
Page Register
A 4-bit register that supports paging.
1. Configures the PSD4XX SRAM to be accessed by
PSEN
as
program space (8031 design).
2. Enables the Peripheral I/O Mode of Port A.
VM
PMMR0
PMMR1
Power management registers; enables the PSD4XX Power Down
Mode and other power saving configurations.
Table 23. Register Function
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