參數(shù)資料
型號(hào)： PSD402A2
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有59個(gè)輸入）
文件頁(yè)數(shù)： 59/97頁(yè)
文件大?。?/td> 309K
代理商： PSD402A2
PSD4XX Famly
4-59
The PSD4XX provides EPROM memory for code storage and SRAM memory for scratch
pad usage. Chip selects for the memory blocks come from the DPLD decoding logic and
are defined by the user in the PSDsoft Software. Figure 31 shows the organization of the
Memory Block.
EPROM
The PSD4XX provides three EPROM densities: 256K bit, 512K bit or 1M bit. The EPROM
is divided into four 8K, 16K or 32K byte blocks. Each block has its own chip select signals
(ES0 – ES3). The EPROM can be configured as 32K x 8, 64K x 8 or 128K x 8 for
microcontrollers with an 8-bit data bus. For 16-bit data buses, the EPROM is configured as
16K x 16, 32K x 16 or 64K x 16.
SRAM
The SRAM has 16K bits of memory, organized as 2K x 8 or 1K x 16. The SRAM is enabled
by chip select signal RS0 from the DPLD. The SRAM has a battery back-up (STBY) mode.
This back-up mode is invoked when the V
CC
voltage drops under the Vstdby voltage by
approximately 0.7 V. The Vstdby voltage is connected only to the SRAM and cannot be
lower than 2.7 volts.
Memory Select Map
The EPROM and SRAM chip select equations are defined in the ABEL file in terms of
address and other DPLD inputs. The memory space for the EPROM chip select
(ES0 – ES3) should not be larger than the EPROM block (8KB, 16KB, or 32KB) it is
selecting.
The following rules govern how the internal PSD4XX memory selects/space are defined:
J
The EPROM blocks address space cannot overlap
J
SRAM, internal I/O and Peripheral I/O space cannot overlap
J
SRAM, internal I/O and Peripheral I/O space can overlap EPROM space, with
priority given to SRAM or I/O. The portion of EPROM which is overlapped
cannot be accessed.
The Peripheral I/O space refers to memory space occupied by peripherals when Port A is
configured in the Peripheral I/O Mode.
Memory
Block
相關(guān)PDF資料
PDF描述
PSD403A1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
PSD403A2 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD411A2 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD412A2 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD413A2 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD402A2-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A2-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A2-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A2-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A2-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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