參數(shù)資料
型號(hào)： PSD211RM
廠商： 意法半導(dǎo)體
英文描述： Low Cost Field Programmable Microcontroller Peripherals
中文描述： 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備
文件頁(yè)數(shù)： 22/51頁(yè)
文件大?。?/td> 348K
代理商： PSD211RM
PSD211R Famly
19
12.
Control Signals
(Cont.)
Signal State Just
After Reset
(Note 1)
Signal State
During Reset
Port
Configured Mode of Operation
AD0/A0-
AD15/A15
All
Input (Hi-Z)
MCU address
and/or data
Input (Hi-Z)
MCU I/O
Input (Hi-Z)
Port Pins
PA0-PA7
PSD211R,
ZPSD211R
ZPSD211RV
Logic 0
MCU address
Latched Address Out
Hi-Z
MCU address
Input (Hi-Z)
MCU I/O
Input (Hi-Z
Chip Select Outputs,
CS0-CS7, CMOS
PSD211R,
ZPSD211R
ZPSD211RV
PSD211R,
ZPSD211R
ZPSD211RV
Logic 1
Per CS equations
Port Pins
PB0-PB7
Hi-Z
Per CS equations
Chip Select Outputs,
CS0-CS7, Open Drain
Hi-Z
Per CS equations
Hi-Z
Per CS equations
Input (Hi-Z)
Address or Logic Inputs, A16-A18
Input (Hi-Z)
Port Pins
PC0-PC2
Chip Select Outputs,
CS8-CS10, CMOS
PSD211R,
ZPSD211R
ZPSD211RV
Logic 1
Per CS equations
Hi-Z
Per CS equations
Table 8A. External PSDSignal States During and Just After Reset
NOTE:
1. Signal is valid immediately after reset for non-V devices. ZPSD211RV devices need an additional
500 nsec after reset before signal is valid.
Internal
Signal State
During
Power-Down
Internal Signal
State During
Reset
Component
Internal Signal
CS0-CS10
Logic 1 (inactive)
Per CS Equations
Per equations
for each
internal signal
PAD A and PAD B
CSIOPORT,
ES0-ES7
Logic 0 (inactive)
All registers in CSIOPORT
address space, including:
Direction
Data
PMR (turbo bit, ZPSD only)
N/A
Logic 0 in all bit of
all registers
Logic 0 until
changed by MCU
Table 8B. Internal PSDSignal States During and Just After Reset
NOTE:
N/A = Not Applicable
RESET LOW
V
IH
RESET HIGH
ZPSD211R(V)
IS OPERATIONAL
500 ns
500 ns
V
IL
Figure 8. The Required Reset Cycle for ZPSD211RV Devices Only.
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