參數(shù)資料
型號: PS7500FE
英文描述: High-Performance, System-on-a-Chip with CRT/LCD Controller|Media Decoders|ARM Processors
中文描述: 高性能,系統(tǒng)上與CRT顯示器芯片/ LCD控制器|媒體解碼器| ARM處理器
文件頁數(shù): 3/4頁
文件大小: 53K
代理商: PS7500FE
CL-PS7500FE
System-on-a-Chip with CRT/LCD Controller
For high performance, the built-in memory controller
in the CL-PS7500FE supports EDO DRAMs.
DRAMs can interface directly to the CL-PS7500FE
in up to 4 separate banks for maximum design flex-
ibility.
Speed Grades
The CL-PS7500FE is available in two speed
grades:
G
ARM CPU running at 40 MHz; memory clock
running up to 64 MHz
G
ARM CPU running at 56 MHz; memory clock
running up to 64 MHz
Packaging
The CL-PS7500FE is available in a 240-pin MQFP
package.
ARM
Compatibility
The ARM processor architecture is quickly becom-
ing the industry’s 32-bit standard. Investment pro-
tection in software and hardware designs is insured
with over 30 companies building products based on
this open, standard processor core. In addition, a
wide range of realtime kernels, sophisticated oper-
ating systems, and state-of-the-art application
development tools are available from third parties
worldwide.
System Design
As shown in the system block diagram below, simply
adding desired memory and peripherals to the
highly integrated CL-PS7500FE completes a high-
performance system board. All the interface logic is
integrated on-chip.
A CL-PS7500FE–Based System
COLOR LCD
SVGA MONITOR
TV
HEADPHONES
CL-PS7500FE
240-PIN PQFP
2*PS/2 PORTS
2 ANALOG
INPUTS
VIDEO O/P
(RGB)
AUDIO O/P
(32 BIT)
KEYBOARD
MOUSE
GAMES DEVICE
(ANALOG)
FRONT PANEL:
STATUS LEDs
RUN/STANDBY SW
REALTIME CLOCK
CONFIG. MEMORY
(NON-VOL.)
DRAM
(4 MBYTE, TYP)
ROM
MODEM
ETHERNET
CS89XX
ENCODER
PAL/NTSC
MEMORY BUS
I/O PORT
CD-DAC
CS4333
ISA-STYLE
BUS
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