
CL-PS7500FE
System-on-a-Chip with CRT/LCD Controller
OVERVIEW
(cont.)
— 4 Kbytes of unified cache
— MMU with 64-entry TLB (transition look-aside buffer)
— 8-words-deep write buffer
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Hardware FPU
— Implements ANSI/IEEE Std. 754-1985
— Single, double, and extended precision
— Up to 12 Mflops, double-precision FP
— Ideal for Java
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DRAM controller
— Supports EDO and Fast Page Mode DRAMs
— Up to 132 Mbps (peak) throughput using 64-MHz
memory clock and 32-bit-wide DRAMs
— Programmable 16- or 32-bit-wide memory system
— Pipelined speed-critical paths
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ROM/FLASH memory control
— Supports two 16-Mbyte banks
— Individual read timings
— Burst mode reads
— Allows for writes under register control for FLASH
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Two PS/2
-style serial ports
— Keyboard
— Mouse
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16-bit ISA-style I/O bus
— Allows for connection to industry-standard peripheral
devices
— CS89XX Ethernet controller
— 56K Fax/modem chipset
— Can be expanded to 32 bits with external transceivers
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Serial CD-quality digital sound (32-bit) output
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Three-state power management
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Eight general-purpose I/O lines
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Four analog comparators
— Supports analog joystick
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Timer and counters
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Available in 40- and 56-MHz speed grades
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240-pin MQFP package
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Evaluation kit available with BOM, schematics,
and design database
In addition to the 32-bit processor with a hardware
floating point unit, the CL-PS7500FE incorporates
system cache, a MMU (memory management unit),
a high-resolution color CRT/LCD graphics control-
ler, a CD-quality audio controller, and various other
peripheral interfaces.
Display Interface
The display controller section of the CL-PS7500FE
features direct drive of an RGB color monitor or a
color LCD. It supports up to a 120-MHz pixel clock
rate for flicker-free screen refreshes at resolutions
up to the XGA 1024 x 768. It also incorporates vari-
ous sync signals; when combined with an external
encoder device, these signals permit the use of
interlaced television monitors for display. A hard-
ware cursor is supported in all display modes to min-
imize system overhead during cursor updates.
The CL-PS7500FE makes use of an UMA (unified
memory architecture) that allows for a design to
share system memory between the display function
and the program memory. This eliminates the need
for separate memory blocks for display and program
memory and reduces overall system costs. A dedi-
cated high-speed DMA channel is used to control
screen updates and minimize the overall system
bandwidth devoted to display requirements.
I/O and Memory
In addition to the advanced peripherals incorporated
into the CL-PS7500FE, a wide variety of Cirrus
Logic and industry-standard third-party peripheral
functions can be attached through the
CL-PS7500FE’s integrated 16-bit ISA-style I/O bus
and eight general-purpose I/O signals. Peripherals
such as modems, mass storage subsystems, CCD
cameras, data acquisition subsystems, and bar
code readers can easily be interfaced to the
CL-PS7500FE through these connections. For
example, the Cirrus Logic CS8900A Ethernet con-
troller can be easily attached for high-speed network
communications. The device also has direct con-
nections for a PS/2-style keyboard and a mouse as
well as a serial CD-quality stereo audio output.
FEATURES
(cont.)