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參數(shù)資料
| 型號： | PS12013-A |
| 廠商： | Powerex Power Semiconductors |
| 英文描述： | FLAT-BASE TYPE INSULATED TYPE |
| 中文描述： | 平性基地型絕緣型 |
| 文件頁數(shù)： | 6/6頁 |
| 文件大小： | 387K |
| 代理商： | PS12013-A |
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12013-A
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
U
P
,V
P
,W
P
,U
N
,V
N
,W
N
,Br
F
O1
,F
O2
,F
O3
,CL
CU,CV,CW
GND(Logic)
V
DL
(5V)
ASIPM
CPU
10k
5.1k
0.1nF
R
R
0.1nF
on
on
on
on
0
0
0
V
PN
DC-Bus voltage
Control voltage supply
Boot-strap voltage
N-Side input signal
P-Side input signal
Brake input signal
F
O
1 output signal
V
DB
V
CIN(N)
V
CIN(P)
V
CIN(Br)
F
OI
V
DH, DL
b)
a)
PWM starts
N-side IGBT Current
N-side FWDi Current
t(hold)
td(read)
Delay time
+I
CL
–I
CL
on
off
on
off
0
0
on
off
0
Ref
V
CIN
V(hold)
I
C
(V
S
)
V
C
V
CL
Fig. 9 START-UP SEQUENCE
Normally at start-up, Fo and CL output signals will be pulled-up
High to V
DL
voltage (OFF level); however, F
O1
output may fall to
Low (ON) level at the instant of the first ON input pulse to an N-Side
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. F
O1
resetting sequence (together with the boot-strap
charging sequence) is explained in the following graph
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
a) Boot-strap charging scheme :
Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20
μ
s number of pulses =10 ~ 500 de-
pending on the boot-strap capacitor size)
b) F
O1
resetting sequence:
Apply ON signals to the following input pins : Br
→
Un/Vn/Wn
→
Up/Vp/Wp in that order.
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART.
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