VSS_ADC
參數(shù)資料
型號： PPC5606BCLU64
廠商： Freescale Semiconductor
文件頁數(shù)： 44/112頁
文件大?。?/td> 0K
描述： MCU 32BIT 1M 64MHZ
標(biāo)準(zhǔn)包裝： 40
系列： MPC56xx Qorivva
核心處理器： e200z0h
芯體尺寸： 32-位
速度： 64MHz
連通性： CAN，I²C，LIN，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 149
程序存儲器容量： 1MB（1M x 8）
程序存儲器類型： 閃存
EEPROM 大小： 4K x 16
RAM 容量： 80K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 29x10b，5x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 176-LQFP
包裝： 托盤
Electrical characteristics
MPC5607B Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
37
VSS_ADC
SR Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC reference) pin with
respect to ground (VSS)
—VSS 0.1
VSS +0.1
V
VDD_ADC
4
SR Voltage on VDD_HV_ADC0,
VDD_HV_ADC1 (ADC reference) with
respect to ground (VSS)
—3.05
3.6
V
Relative to VDD
VDD 0.1 VDD +0.1
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS)
—VSS 0.1
—
V
Relative to VDD
—VDD +0.1
IINJPAD
SR Injected input current on any pin during
overload condition
—
55
mA
IINJSUM
SR Absolute sum of all injected input currents
during overload condition
—
50
TVDD
SR VDD slope to ensure correct power up
6
—
0.25
V/s
TA C-Grade Part
SR Ambient temperature under bias
fCPU 64 MHz
7
40
85
°C
TJ C-Grade Part
SR Junction temperature under bias
—
40
110
TA V-Grade Part
SR Ambient temperature under bias
fCPU 64 MHz
40
105
TJ V-Grade Part
SR Junction temperature under bias
—
40
130
TA M-Grade Part
SR Ambient temperature under bias
fCPU 64 MHz
40
125
TJ M-Grade Part
SR Junction temperature under bias
—
40
150
1 100 nF capacitance needs to be provided between each V
DD/VSS pair.
2 330 nF capacitance needs to be provided between each V
DD_LV/VSS_LV supply pair.
3 470 nF capacitance needs to be provided between V
DD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). Supply ramp slope on VDD_BV should always be faster or equal
to slope of VDD_HV. Otherwise, device may enter regulator bypass mode if slope on VDD_BV is slower.
4 100 nF capacitance needs to be provided between V
DD_ADC/VSS_ADC pair.
5 Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL,
device is reset.
6 Guaranteed by device validation
7 When the FMPLL uses the frequency modulation with a modulation depth of 4% from the center spread frequency,
the maximum value of fCPU is 66.56 MHz.
Table 13. Recommended operating conditions (5.0 V)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
V
VDD
1
SR Voltage on VDD_HV pins with respect to ground
(VSS)
—4.5
5.5
V
Voltage drop2
3.0
5.5
Table 12. Recommended operating conditions (3.3 V) (continued)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
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