參數(shù)資料
型號(hào)： PPC440GR-3pbfffCx
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁數(shù)： 75/82頁
文件大?。?/td> 527K
代理商： PPC440GR-3PBFFFCX
AMCC Proprietary
75
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Revision 1.16 – July 19, 2006
Figure 10. DDR SDRAM Read Data Path
Table 23. I/O Timing—DDR SDRAM T
SIN
and T
DIN
Notes:
1. T
SIN
= Delay from DQS at package pin to C on Stage 1 FF.
2. T
DIN
= Delay from data at package pin to D on Stage 1 FF.
3. Clock speed for the values in the table is 133MHz.
4. The time values for T
SIN
include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a
slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the eight DQS signals be matched.
Signal Name
T
SIN
(ns)
minimum
2.74
2.75
2.74
2.76
2.77
T
SIN
(ns)
maximum
3.70
3.69
3.69
3.69
3.68
Signal Name
T
DIN
(ns)
minimum
0.86
0.87
0.89
0.88
0.89
T
DIN
(ns)
maximum
1.87
1.86
1.86
1.85
1.83
DQS0
DQS1
DQS2
DQS3
DQS8
MemData00:07
MemData08:15
MemData16:23
MemData24:31
ECC0:7
Stage 1
Stage 2
Stage 3
RDSP
PLB bus
FF,
XL
FF
FF
FF
Data
Read Select
(SDRAM0_TR1)
DQS
1/4
Cycle
Delay
PLB Clock
Programmed
Read Clock
Delay
D
C
Package pins
Mux
C
C
C
D
D
D
FF Timing:
T
IS
= Input setup time = 0.2ns
T
IH
= Input hold time = 0.1ns
T
P
= Propagation delay (D to Q or C to Q) = 0.4ns maximum
ECC
FF: Flip-Flop
XL: Transparent Latch
Q
Q
Q
Q
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參數(shù)描述
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