參數(shù)資料
型號(hào)： PPC440GR-3pbfffCx
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁數(shù)： 65/82頁
文件大?。?/td> 527K
代理商： PPC440GR-3PBFFFCX
AMCC Proprietary
65
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Revision 1.16 – July 19, 2006
I/O Specifications
Table 16. Peripheral Interface Clock Timings
Parameter
Min
Max
Units
Notes
PCIClk input frequency (asynchronous mode)
–
66.66
MHz
PCIClk period (asynchronous mode)
15
–
ns
PCIClk input high time
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
–
2.5
MHz
EMCMDClk period
400
–
ns
EMCMDClk output high time
160
–
ns
EMCMDClk output low time
160
–
ns
EMCTxClk input frequency MII(RMII)
2.5(5)
25(50)
MHz
EMCTxClk period MII(RMII)
40(20)
400(200)
ns
EMCTxClk input high time
35% of nominal period
–
ns
EMCTxClk input low time
35% of nominal period
–
ns
EMCRxClk input frequency MII(RMII)
2.5(5)
25(50)
MHz
EMCRxClk period MII(RMII)
40(20)
400(200)
ns
EMCRxClk input high time
35% of nominal period
–
ns
EMCRxClk input low time
35% of nominal period
–
ns
PerClk (and OPB Clock) output frequency (for ext. master or
sync. slaves)
–
66.66
MHz
PerClk period
15
–
ns
PerClk output high time
50% of nominal period
66% of nominal period
ns
PerClk output low time
33% of nominal period
50% of nominal period
ns
UARTSerClk input frequency
–
1000/(2T
OPB1
+2ns)
MHz
1
UARTSerClk period
2T
OPB
+2
–
ns
1
UARTSerClk input high time
T
OPB
+1
–
ns
1
UARTSerClk input low time
T
OPB
+1
–
ns
1
TmrClk1 input frequency
–
100
MHz
2
TmrClk1 period
10
–
ns
TmrClk1 input high time
40% of nominal period
60% of nominal period
ns
TmrClk1 input low time
40% of nominal period
60% of nominal period
ns
Notes:
1. T
OPB
is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock
frequency is 66.66 MHz.
2. See Table 7 for information on the TmrClk2 signal.
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