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參數(shù)資料
| 型號： | PLUS405-55A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Programmable logic sequencer 16 】 64 】 8 |
| 中文描述： | OT PLD, 8 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 327K |
| 代理商： | PLUS405-55A |
Philips Semiconductors
Product specification
PLUS405-37/-45
Programmable logic sequencers
(16
×
64
×
8)
1996 Nov 12
4
TRUTH TABLE
1, 2, 3, 4, 5, 6, 7
OPTION
V
CC
INIT
OE
I10
I11
I12
CK
J
K
Q
P
H/L
Q
P
Q
P
L
H
Q
P
Q
P
Q
P
Q
P
Q
P
L
H
Q
P
Q
P
Q
P
L
H
Q
P
Q
F
H/L
L
H
Q
F
Q
F
Q
F
Q
F
Q
F
L
H
Q
F
Q
F
Q
F
Q
F
Q
F
L
H
Q
F
F
H
L
L
L
L
L
L
*
*
X
X
*
X
X
X
X
X
↑
↑
↑
↑
X
X
X
↑
↑
↑
↑
X
X
↑
↑
↑
↑
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
H
Q
F
L
H
L
H
Q
P
Q
F
Hi-Z
L
H
L
H
Q
P
Q
F
Q
F
L
H
Q
F
+10V
+10V
X
X
X
X
X
+10V
+10V
X
X
X
X
X
X
X
X
+10V
+10V
X
X
X
X
X
+10V
+10V
X
X
X
X
X
X
+10V
X
*
X
X
X
X
+10V
X
X
X
X
X
H
X
X
X
X
L
L
L
L
L
L
+5V
↑
X
X
X
X
X
X
X
X
H
H
NOTES:
1. Positive Logic:
S/R (or J/K) = T
0
+ T
1
+ T
2
+ . . . T
63
T
n
= (C0, C1) (I0, I1, I2, . . .) (P0, P1, . . . P7)
2. Either Initialization (Active-High) or Output Enable (Active-Low) are available, but not both. The desired function is a user-programmable
option.
3.
↑
denotes transition from Low-to-High level.
4. * = H or L or +10V
5. X = Don’t Care (<5.5V)
6. H/L implies that either a High or a Low can occur, depending upon user-programmed selection (each State and Output Register individually
programmable).
7. When using the F
n
pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels
on the output pins are forced by the user.
VIRGIN STATE
A factory-shipped virgin device contains all fusible links intact, such
that:
1. INIT/OE is set to INIT. In order to use the INIT function, the user
must select either the PRESET or the RESET option for each
flip-flop. Note that regardless of the user-programmed
initialization, or even if the INIT function is not used, all registers
are preset to “1” by the power-up procedure.
2. All transition terms are inactive (0).
3. All S/R (or J/K) flip-flop inputs are disabled (0).
4. The device can be clocked via a Test Array preprogrammed with
a standard test pattern.
5. Clock 2 is inactive.
LOGIC FUNCTION
0
1
0
0
0
1
STATE REGISTER
S
R
S
n + 1
PRESENT STATE
A
B
C
. . .
NEXT STATE
Q2
Q1
Q0
SET Q
0
: J
0
= (Q
2
Q
1
Q
0
)
A
B
C . . .
K
0
= 0
RESET Q
1
: J
1
= 0
K
1
= (Q
3
Q
2
Q
1
Q
0
)
A
B
C . . .
HOLD Q
2
: J
2
= 0
K
2
= 0
1
0
Q3
RESET Q
3
: J
3
= (Q
3
Q
2
Q
1
Q
0
)
A
B
C . . .
K
3
= (Q
3
Q
2
Q
1
Q
0
)
A
B
C . . .
SP00231
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