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參數(shù)資料
| 型號： | PLUS405-55A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Programmable logic sequencer 16 】 64 】 8 |
| 中文描述： | OT PLD, 8 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 327K |
| 代理商： | PLUS405-55A |
Philips Semiconductors
Product specification
PLUS405-37/-45
Programmable logic sequencers
(16
×
64
×
8)
1996 Nov 12
13
TIMING DEFINITIONS
SYMBOL
PARAMETER
t
CKH1, 2
Width of input clock pulse.
t
CKP1, 2
Minimum guaranteed clock period.
t
IS1
Required delay between beginning of valid input and positive transition of Clock.
t
CKO1, 2
Delay between positive transition of Clock and when Outputs become valid (with INIT/OE Low).
t
PPR
Delay between V
CC
(after power–on) and when Outputs become preset at “1”.
t
IS2
Required delay between beginning of valid Input and positive transition of Clock, when using optional Complement Array (two
passes necessary through the AND Array).
t
RJH
Required delay between positive transition of clock, and return of input I10, I11 or I12 from Diagnostic Mode (10V).
f
MAX1, 2
Minimum guaranteed operating frequency; input to output (CLK1 and CLK2).
f
MAX3, 4
Minimum guaranteed operating frequency; input through Complement Array, to output (CLK1 and CLK2).
f
MAX5
Minimum guaranteed internal operating frequency; with internal feedback from state register to state register.
f
MAX6
Minimum guaranteed internal operating frequency with Complement Array, with internal feedback from state register through
Complement Array, to state register.
f
CLK
Minimum guaranteed clock frequency (register toggle frequency).
t
CKL1, 2
Interval between clock pulses.
t
IH
Required delay between positive transition of Clock and end of valid Input data.
t
Delay between beginning of Output Enable Low and when Outputs become valid.
t
SRE
Delay between input I12 transition to Diagnostic Mode and when the Outputs reflect the contents of the State Register.
t
RJS
Required delay between inputs I11, I10 or I12 transition to Diagnostic Mode (10V), and when the output pins become available
as inputs.
t
NVCK
Required delay between the negative transition of the clock and the negative transition of the Asynchronous Initialization to
guarantee that the clock edge is not detected as a valid negative transition.
t
INITH
Width of initialization input pulse.
t
VS
Required delay between V
CC
(after power–on) and negative transition of Clock preceding first reliable clock pulse.
t
OD
Delay between beginning of Output Enable High and when Outputs are in the OFF–state.
t
INIT
Delay between positive transition of Initialization and when Outputs become valid.
t
SRD
Delay between input I12 transition to Logic mode and when the Outputs reflect the contents of the Output Register.
t
RH
Required delay between positive transition of Clock and end of valid Input data when jamming data into State or Output
Registers in diagnostic mode.
t
VCK
Required delay between negative transition of Asynchronous Initialization and negative transition of Clock preceding first
reliable clock pulse.
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