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參數資料
| 型號： | PLUS405-55 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable logic sequencer 16 】 64 】 8 |
| 中文描述： | 可編程序邏輯16】64】8 |
| 文件頁數： | 3/20頁 |
| 文件大?。?/td> | 327K |
| 代理商： | PLUS405-55 |
Philips Semiconductors
Product specification
PLUS405-37/-45
Programmable logic sequencers
(16
×
64
×
8)
1996 Nov 12
3
ORDERING INFORMATION
DESCRIPTION
OPERATING
FREQUENCY
ORDER CODE
DRAWING NUMBER
28-Pin Plastic DIP (600mil-wide)
45MHz (t
IS1
+ t
CKO1
)
37MHz (t
IS1
+ t
CKO1
)
45MHz (t
IS1
+ t
CKO1
)
37MHz (t
IS1
+ t
CKO1
)
PLUS405–45N
SOT117-2
28-Pin Plastic DIP (600mil-wide)
PLUS405–37N
SOT117-2
28-Pin Plastic Leaded Chip Carrier
PLUS405–45A
SOT261-3
28-Pin Plastic Leaded Chip Carrier
PLUS405–37A
SOT261-3
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
POLARITY
1
CLK1
Clock:
The Clock input to the State and Output Registers. A Low-to-High transition on this
line is necessary to update the contents of both state and output registers. Pin 1 only
clocks P0–3 and F0–3 if Pin 4 is also being used as a clock.
Active-High (H)
2, 3, 5–9,
26–27
20–22
I0–I4, I7, I6
I8–I9
I13–I15
Logic Inputs:
The 12 external inputs to the AND array used to program jump conditions
between machine states, as determined by a given logic sequence. True and complement
signals are generated via use of “H” and “L”.
Active-High/Low
(H/L)
4
CLK2
Logic Input/Clock:
A user programmable function:
Logic Input:
A 13th external logic input to the AND array, as above.
Active-High/Low
(H/L)
Clock:
A 2nd clock for the State Registers P4–7 and Output Registers F4–7, as above.
Note that input buffer I
must be deleted from the AND array (i.e., all fuse locations “Don’t
Care”) when using Pin 4 as a Clock.
Active-High (H)
23
I12
Logic/Diagnostic Input:
A 14th external logic input to the AND array, as above, when
exercising standard TTL or CMOS levels. When I12 is held at +10V, device outputs F0–F7
reflect the contents of State Register bits P0–P7. The contents of each Output Register
remains unaltered.
Active-High/Low
(H/L)
24
I11
Logic/Diagnostic Input:
A 15th external logic input to the AND array, as above, when
exercising standard TTL levels. When I11 is held at +10V, device outputs F0–F7 become
direct inputs for State Register bits P0–P7; a Low-to-High transition on the appropriate
clock line loads the values on pins F0–F7 into the State Register bits P0–P7. The contents
of each Output Register remains unaltered.
Active-High/Low
(H/L)
25
I10
Logic/Diagnostic Input:
A 16th external logic input to the AND array, as above, when
exercising standard TTL levels. When I
10
is held at +10V, device outputs F0–F7 become
direct inputs for Output Register bits Q0–Q7; a Low-to-High transition on the appropriate
clock line loads the values on pins F0–F7 into the Output Register bits Q0–Q7. The con-
tents of each State Register remains unaltered.
Active-High/Low
(H/L)
10–13
15–18
F0 – F7
Logic Outputs/Diagnostic Outputs/Diagnostic Inputs:
Eight device outputs which nor-
mally reflect the contents of Output Register Bits Q0–Q7, when enabled. When I12 is held
at +10V, F0–F7 = (P0–P7). When I11 is held at +10V, F0–F7 become inputs to State Reg-
ister bits P0–P7. When I10 is held at +10V, F0–F7 become inputs to Output Register bits
Q0–Q7.
Active-High (H)
19
INIT/OE
Initialization or Output Enable Input:
A user programmable function:
Initialization:
Provides an asynchronous preset to logic “1” or reset to logic “0” of all
State and Output Register bits, determined individually for each register bit through user
programming. INIT overrides Clock, and when held High, clocking is inhibited and F0–F7
and P0–P7 are in their initialization state. Normal clocking resumes with the first full clock
pulse following a High-to-Low clock transition, after INIT goes Low. See timing definition for
t
NVCK
and t
VCK
.
Output Enable:
Provides an output enable function to buffers F0–F7 from the Output
Registers.
Active-High (H)
Active-Low (L)
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PDF描述 |
|---|---|
| PLUS405-55A | Programmable logic sequencer 16 】 64 】 8 |
| PLUS405-55N | Programmable logic sequencer 16 】 64 】 8 |
| PM5S | TEMPORIZZATORI PER GUIDA DIN |
| PM5S-A | TEMPORIZZATORI PER GUIDA DIN |
| PM5S-M | TEMPORIZZATORI PER GUIDA DIN |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PLUS405-55A | 制造商:NXP Semiconductors 功能描述:Simple, Programmable Logic Sequencer, 28 Pin, Plastic, PLCC |
| PLUS405-55N | 制造商:NXP Semiconductors 功能描述:Simple, Programmable Logic Sequencer, 28 Pin, Plastic, DIP |
| PLUS405AA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| PLUS405AN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| PLUS48-LEVEL1/VIS | 制造商:Misc 功能描述: |
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