參數(shù)資料
型號: PLUS405-55
廠商: NXP Semiconductors N.V.
英文描述: Programmable logic sequencer 16 】 64 】 8
中文描述: 可編程序邏輯16】64】8
文件頁數(shù): 2/20頁
文件大?。?/td> 327K
代理商: PLUS405-55
Philips Semiconductors
Product specification
PLUS405-37/-45
Programmable logic sequencers
(16
×
64
×
8)
2
1996 Nov 12
853–1280 17500
DESCRIPTION
The PLUS405 devices are bipolar, programmable state machines of
the Mealy type. Both the AND and the OR array are
user-programmable. All 64 AND gates are connected to the 16
external dedicated inputs (I0 - I15) and to the feedback paths of the
8 on-chip State Registers (Q
P0
- Q
P7
). Two complement arrays
support complex IF-THEN-ELSE state transitions with a single
product term (input variables C0, C1)
.
All state transition terms can include True, False and Don’t Care
states of the controlling state variables. All AND gates are merged
into the programmable OR array to issue the next-state and
next-output commands to their respective registers. Because the
OR array is programmable, any one or all of the 64 transition terms
can be connected to any or all of the State and Output Registers.
All state (Q
P0
- Q
P7
) and output (Q
F0
- Q
F7
) registers are
edge-triggered, clocked J-K flip-flops, with Asynchronous Preset and
Reset options. The PLUS405 architecture provides the added
flexibility of the J-K toggle function which is indeterminate on S-R
flip-flops. Each register may be individually programmed such that a
specific Preset-Reset pattern is initialized when the initialization pin
is raised to a logic level “1”. This feature allows the state machine to
be asynchronously initialized to known internal state and output
conditions, prior to proceeding through a sequence of state
transitions. Upon power-up, all registers are unconditionally preset
to “1”. If desired, the initialization input pin (INIT) can be converted to
an Output Enable (OE) function as an additional user-programmable
feature.
Availability of two user-programmable clocks allows the user to
design two independently clocked state machine functions
consisting of four state and four output bits each.
Order codes are listed in the Ordering Information Table.
FEATURES
PLUS405-37
f
MAX
= 37MHz
50MHz clock rate
PLUS405-45
f
MAX
= 45MHz
58.8MHz clock rate
Functional superset of PLS105/105A
Field-programmable (Ti-W fusible link)
16 input variables
8 output functions
64 transition terms
8-bit State Register
8-bit Output Register
2 transition Complement Arrays
Multiple clocks*
Programmable Asynchronous Initialization or Output Enable
Power-on preset of all registers to “1”
“On-chip” diagnostic test mode features for access to state and
output registers
950mW power dissipation (typ.)
TTL compatible
J-K or S-R flip-flop functions
Automatic “Hold” states
3-State outputs
APPLICATIONS
Interface protocols
Sequence detectors
Peripheral controllers
Timing generators
Sequential circuits
Elevator contollers
Security locking systems
Counters
Shift registers
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
N Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CLK
I7
I6
I5/CLK
I4
I3
I2
I1
I0
F7
F6
F5
F4
GND
F3
F2
F1
F0
INIT/OE
I15
I14
I13
I12
I11
I10
I9
I8
V
CC
CLK
I6
I7
V
CC
I5/CLK
I8
I9
I4
I3
I2
I1
I0
F7
F6
F5
F4 GND F3
F2
F1
F0
INIT/OE
I15
I14
I13
I12
I11
I10
N = Plastic DIP (600mil-wide)
A = Plastic Leaded Chip Carrier
A Package
SP00251
相關(guān)PDF資料
PDF描述
PLUS405-55A Programmable logic sequencer 16 】 64 】 8
PLUS405-55N Programmable logic sequencer 16 】 64 】 8
PM5S TEMPORIZZATORI PER GUIDA DIN
PM5S-A TEMPORIZZATORI PER GUIDA DIN
PM5S-M TEMPORIZZATORI PER GUIDA DIN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PLUS405-55A 制造商:NXP Semiconductors 功能描述:Simple, Programmable Logic Sequencer, 28 Pin, Plastic, PLCC
PLUS405-55N 制造商:NXP Semiconductors 功能描述:Simple, Programmable Logic Sequencer, 28 Pin, Plastic, DIP
PLUS405AA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD
PLUS405AN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD
PLUS48-LEVEL1/VIS 制造商:Misc 功能描述: