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參數(shù)資料
| 型號： | PLS101 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable logic arrays 16 】 48 】 8 |
| 中文描述： | 可編程邏輯陣列16】48】8 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 127K |
| 代理商： | PLS101 |
Philips Semiconductors Programmable Logic Devices
Product specification
PLS100/PLS101
Programmable logic arrays
(16
×
48
×
8)
October 22, 1993
54
LOGIC PROGRAMMING
PLS100/PLS101 is fully supported by
industry standard (JEDEC compatible) PLD
CAD tools, including Philips Semiconductors’
SNAP, Data I/O Corporation’s ABEL
and
Logical Devices Inc.’s CUPL
design
software packages.
All packages allow Boolean and state
equation entry formats. SNAP, ABEL and
CUPL also accept, as input, schematic
capture format.
OUTPUT POLARITY – (F)
PLS100/PLS101 logic designs can also be
generated using the program table entry
format detailed on the following pages. This
program table entry format is supported by
the Philips Semiconductors’ SNAP PLD
design software package.
To implement the desired logic functions, the
state of each logic variable from logic
equations (I, B, O, P, etc.) is assigned a
symbol. The sumbols for TRUE,
COMPLEMENT, INACTIVE, PRESET, etc.,
are defined below.
PROGRAMMING AND
SOFTWARE SUPPORT
Refer to Section 9
(Development Software)
and Section 10
(Third-party Programmer/
Software Support)
of this dat handbook for
additional informational.
CODE
ACTIVE LEVEL
HIGH
1
(NON-INVERTING)
LOW
(INVERTING)
H
S
X
O, B
CODE
ACTIVE LEVEL
L
S
F
“AND” ARRAY – (I)
CODE
STATE
INACTIVE
1,2
O
P
I
I
I
CODE
–
STATE
DON’T CARE
CODE
STATE
CODE
STATE
I
H
L
P
I
I
I
P
I
I
I
P
I
I
I
I
“OR” ARRAY – (F)
CODE
INACTIVE
A
CODE
P
n
STATUS
ACTIVE
1
P
S
P
S
P
n
STATUS
NOTES:
1. This is the initial unprogrammed state of all links. It is normally associated with all unused
(inactive) AND gates P
.
2. Any gate P
n
will be unconditionally inhibited if any one of its (I) link pairs is left intact.
VIRGIN STATE
The PLS100/101 virgin devices are factory
shipped in an unprogrammed state, with all
fuses intact, such that:
1. All P
n
terms are disabled (inactive) in the
AND array.
2. All P
n
terms are active in the OR array.
3. All outputs are Active-High.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
相關PDF資料 |
PDF描述 |
|---|---|
| PLS101A | Programmable logic arrays 16 】 48 】 8 |
| PLS101N | Programmable logic arrays 16 】 48 】 8 |
| PLS168 | FIELD PROGRAMMABLE LOGIC SEQUENCER |
| PLS168-33 | 24-PIN TTL/CMOS PROGRAMMABLE LOGIC SEQUENCERS |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PLS101A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable logic arrays 16 】 48 】 8 |
| PLS101N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable logic arrays 16 】 48 】 8 |
| PLS101N-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| PLS1020ASE7KNA | 制造商:Freescale Semiconductor 功能描述:PLS1020ASE7KNA - Bulk |
| PLS1022ASE7EKA | 制造商:Freescale Semiconductor 功能描述:PLS1022ASE7EKA - Bulk |
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