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參數(shù)資料
| 型號(hào)： | PLS101 |
| 廠(chǎng)商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable logic arrays 16 】 48 】 8 |
| 中文描述： | 可編程邏輯陣列16】48】8 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 127K |
| 代理商： | PLS101 |
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PD
INPUT
F0 – F7
CE
1.5V
1.5V
1.5V
1.5V
1.5V
t
CE
t
CD
V
OL
V
OH
+3.0V
0V
+3.0V
0V
Read Cycle
Philips Semiconductors Programmable Logic Devices
Product specification
PLS100/PLS101
Programmable logic arrays
(16
×
48
×
8)
October 22, 1993
53
AC ELECTRICAL CHARACTERISTICS
0
°
C < T
amb
< +75
°
C, 4.75 < V
CC
< 5.25V, R
1
= 470
, R
2
= 1k
LIMITS
SYMBOL
PARAMETER
TO
FROM
MIN
TYP
1
MAX
UNIT
Propagation delay
2
t
PD
Input
Output
Input
35
50
ns
t
CE
Chip Enable
3
Output
Chip Enable
15
30
ns
Disable time
t
CD
Chip Disable
3
Output
Chip Enable
15
30
ns
NOTES:
1. All typical values are at V
CC
= 5V. T
amb
= +25
°
C.
2. All propagation delays are measured and specified under worst case conditions.
3. For 3-State output; output enable times are tested with C
L
= 30pF to the 1.5V level, and S
1
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L
= 5pF. High-to-High impedance tests are made to an output
voltage of V
T
= (V
OH
– 0.5V) with S
1
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
VOLTAGE WAVEFORMS
TEST LOAD CIRCUIT
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of in-
puts and outputs, unless otherwise specified.
90%
10%
5ns
5ns
5ns
5ns
90%
10%
+3.0V
+3.0V
0V
0V
t
R
t
F
Input Pulses
+5V
C
L
R
1
R
2
S
1
GND
F
7
F
0
INPUTS
I
0
I
15
CE
OUTPUTS
C
2
C
1
DUT
NOTE:
C
1
and C
2
are to bypass V
CC
to GND.
V
CC
TIMING DEFINITIONS
SYMBOL
PARAMETER
t
CE
Delay between beginning of
Chip Enable Low (with Input
valid) and when Data Output
becomes valid.
t
CD
Delay between when Chip
Enable becomes High and
Data Output is in off state
(Hi-Z or High).
t
PD
Delay between beginning of
valid Input (with Chip Enable
Low) and when Data Output
becomes valid.
TIMING DIAGRAM
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