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參數(shù)資料
| 型號(hào)： | PLL1707DBQR |
| 英文描述： | FF-SM Series, Type 3, Safety Mat, pressure sensitive, 1000 x 500 mm2 [3.28 x 1.64 ft2] dimensions, aluminum coating |
| 中文描述： | 3.3 V雙鎖相環(huán)MULTICLOCK發(fā)生器 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 171K |
| 代理商： | PLL1707DBQR |
SLES065
–
DECEMBER 2002
www.ti.com
10
The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to
XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options,
and Figure 9 illustrates the 27-MHz master clock timing requirement.
Crystal
PLL1707/PLL1708
Crystal
OSC
Circuit
27-MHz
Internal
Master
Clock
XT1
XT2
C2
C1
MCKO1
MCKO2
C1, C2 = 10 pF to 33 pF
Crystal Resonator Connection
PLL1707/PLL1708
XT1
XT2
MCKO1
MCKO2
External Clock Input Connection
External
Clock
Crystal
OSC
Circuit
27-MHz
Internal
Master
Clock
Figure 8. Master Clock Generator Connection Diagram
t(XT1H)
XT1
t(XT1L)
0.7 VCC
0.3 VCC
DESCRIPTION
SYMBOL
t(
XT1H)
t(
XT1L)
MIN
10
10
MAX
UNIT
ns
ns
Master clock pulse duration HIGH
Master clock pulse duration LOW
Figure 9. External Master Clock Timing Requirement
The PLL1707/8 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs
256 f
S,
384 f
S
512 f
S,
or 768 f
S
(f
S
= 48 kHz) which is selected by hardware or software control. The output frequency of
the remaining clocks is determined by the sampling frequency (f
S
) under hardware or software control. SCKO2 and SCKO3
output 256-f
S
and 384-f
S
system clocks, respectively. Table 2 shows each sampling frequency which can be programmed.
The system clock output frequencies for programmed sampling frequencies are shown in Table 3. The half sampling
frequencies on SCKO2 and SCKO3 and 256 f
S
and 384 f
S
on SCKO1 are supported only on the PLL1708.
Table 1. Generated System Clock SCKO1 Frequency
fS
SCKO1 FREQUENCY
12.288 MHz
18.432 MHz
24.576 MHz
36.864 MHz
256 fS
384 fS
512 fS
768 fS
PLL1708 only
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLL1708DBQR | 3.3 V DUAL PLL MULTICLOCK GENERATOR |
| PLL1707 | 3.3 V DUAL PLL MULTICLOCK GENERATOR |
| PLL1708 | 3.3 V DUAL PLL MULTICLOCK GENERATOR |
| PLS100 | Programmable logic arrays 16 】 48 】 8 |
| PLS101 | Programmable logic arrays 16 】 48 】 8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL1707DBQRE4 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1707DBQRG4 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1707IDBQRQ1 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 AC 3.3 V Dual PLL Multi-Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1707-Q1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3-V DUAL-PLL MULTICLOCK GENERATOR |
| PLL1708 | 制造商:BB 制造商全稱:BB 功能描述:3.3 V DUAL PLL MULTICLOCK GENERATOR |
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