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參數(shù)資料
| 型號： | PLL1700 |
| 英文描述： | MULTI-CLOCK GENERATOR |
| 中文描述： | 多時鐘發(fā)生器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 137K |
| 代理商： | PLL1700 |
6
PLL1700
The PLL1700 provides a very low jitter, high accuracy
clock. SCKO1 is a fixed frequency clock which is
33.8688MHz (768 x 44.1kHz) for a CD-DA DSP. The
output frequency of the remaining clocks is determined by
the sampling frequency (f
S
) by software or hardware control.
SCKO2 and SCKO3 output 256f
S
and 384f
S
systems clocks,
respectively. SCKO4 output is 768f
S
if the sampling fre-
quency is 32kHz, 44.1kHz, 48kHz, or the output is 384f
S
if
the sampling frequency is 64kHz, 88.2kHz, or 96kHz. Table
I shows each sampling frequency. The system clock output
frequencies are generated by a 27MHz master clock and
programmed sampling frequencies are shown in Table II.
SAMPLING
FREQUENCY
(kHz)
SAMPLING
RATE
SKCO2
(MHz)
SCKO3
(MHz)
SCKO4
(MHz)
32
44.1
48
Standard
Standard
Standard
8.192
11.2896
12.288
12.288
16.9344
18.4320
24.576
33.8688
36.8640
64
88.2
96
Double
Double
Double
16.384
22.5792
24.576
24.576
33.8688
36.8640
24.576
33.8688
36.8640
TABLE II. Sampling Frequencies and Master Clock Output
Frequencies.
SAMPLING
FREQUENCY (kHz)
SAMPLING RATE
Standard Sampling Frequencies
Double of Standard Sampling Frequencies
32
64
44.1
88.2
48
96
TABLE I. Sampling Frequencies.
FUNCTION CONTROL
The built-in function of the PLL1700 can be controlled in
the software mode (serial mode), which uses a three-wire
interface by ML (pin 1), MC (pin 20), and MD (pin 19),
when MODE (pin 2) = L. They can also be controlled in the
hardware mode (parallel mode) which uses SR0 (pin 1), FS1
(pin 20) and FS0 (pin 19), when MODE (pin 2) = H. The
selectable functions are shown in Table III.
HARDWARE
MODE
(MODE = H)
SOFTWARE
MODE
(MODE = L)
FUNCTION
Sampling Frequency Select
(32kHz, 44.1kHz, 48kHz)
Yes
Yes
Sampling Rate Select (Standard/Double)
Yes
Yes
Each Clock Output Enable/Disable
No
Yes
TABLE III. Selectable Functions.
Response time from power-on (or applying the clock to
XT1) to SCKO settling time is typically 15ms. Delay time
from sampling frequency change to SCKO settling time is
20ms maximum. Figure 4 illustrates SCKO transient timing.
External buffers are recommended on all output clocks in
order to avoid degrading the jitter performance of the
PLL1700.
RESET
The PLL1700 has an internal power-on reset circuit, as well
as an external forced reset (RST, pin 18). Both resets have
the same effect on the PLL1700’s functions. The mode
register’s default settings for software mode are initialized
by reset. Throughout the reset period, all clock outputs are
enabled with the default settings. Initialization for the inter-
nal power-on reset is done automatically during 1024 master
clocks at V
DD
≥
2.2V (1.8V to 2.6V). When using the
internal power-on reset, RST should be HIGH. Power-on
reset timing is shown in Figure 5. RST (pin 18) accepts an
external forced reset by RST = L. Initialization (reset) is
done when RST = L and 1024 master clocks after RST =
H. External reset timing is shown in Figures 6 and 7.
FUNCTION
DEFAULT
Sampling Frequency Select (32kHz, 44.1kHz, 48kHz)
Sampling Rate Select (Standard/Double)
Each Clock Output Enable/Disable
48kHz Group
Standard
Enable
TABLE IV. Selectable Functions.
FS1 (Pin 20)
FS0 (Pin 19)
SAMPLING GROUP
L
L
H
H
L
H
L
H
48kHz
44.1kHz
32kHz
Reserved
SR0 (Pin 1)
SAMPLING RATE SELECT
L
H
Standard
Double
HARDWARE MODE (MODE = H)
In the hardware mode, the following functions can be
selected:
Sampling Group Select
The sampling frequency group can be selected by FS1 (pin
20) and FS0 (pin 19).
Sampling Rate Select
The sampling rate can be selected by SR0 (pin 1)
SOFTWARE MODE (MODE = L)
The PLL1700’s special function in software mode is shown
in Table IV. These functions are controlled using ML, MC,
and MD serial control signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL1700E | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3 V Dual PLL Multi Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1700E/2K | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1700E/2KG4 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1700EG | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1700EG/2K | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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