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參數(shù)資料
型號: PK30X256VMD100
廠商: Freescale Semiconductor
文件頁數(shù): 54/74頁
文件大小: 0K
描述: IC ARM CORTEX MCU 256K 144-MAP
產(chǎn)品培訓(xùn)模塊: Kinetis® Cortex-M4 Microcontroller Family
標準包裝: 1
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,IrDA,SDHC,SPI,UART/USART
外圍設(shè)備: DMA,I²S,LCD,LVD,POR,PWM,WDT
輸入/輸出數(shù): 102
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 37x16b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LBGA
包裝: 托盤
SD2
SD3
SD1
SD6
SD8
SD7
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 24. SDHC timing
6.8.7 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 44. I2S master mode timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
2 x tSYS
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_BCLK cycle time
5 x tSYS
ns
S4
I2S_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_BCLK to I2S_FS output valid
15
ns
S6
I2S_BCLK to I2S_FS output invalid
-2.5
ns
S7
I2S_BCLK to I2S_TXD valid
15
ns
S8
I2S_BCLK to I2S_TXD invalid
-3
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
20
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
ns
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
58
Freescale Semiconductor, Inc.
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