Table 28. 16-bit ADC characteristics (VREFH = VDDA
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Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
Description
Min.
Typ.2
Max.
Unit
Notes
fADACK
ADC
asynchronous
clock source
ADLPC = 1, ADHSC = 0
ADLPC = 1, ADHSC = 1
ADLPC = 0, ADHSC = 0
ADLPC = 0, ADHSC = 1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
tADACK = 1/
fADACK
Sample Time
See Reference Manual chapter for sample times
TUE
Total unadjusted
error
12-bit modes
<12-bit modes
鈥�
卤4
卤1.4
卤6.8
卤2.1
LSB4
DNL
Differential non-
linearity
12-bit modes
<12-bit modes
鈥�
卤0.7
卤0.2
-1.1 to +1.9
-0.3 to 0.5
LSB4
INL
Integral non-
linearity
12-bit modes
<12-bit modes
鈥�
卤1.0
卤0.5
-2.7 to +1.9
-0.7 to +0.5
LSB4
EFS
Full-scale error
12-bit modes
<12-bit modes
鈥�
-4
-1.4
-5.4
-1.8
LSB4
VADIN =
VDDA
EQ
Quantization
error
16-bit modes
鈮�13-bit modes
鈥�
-1 to 0
鈥�
卤0.5
LSB4
ENOB
Effective number
of bits
16-bit differential mode
Avg = 32
Avg = 4
16-bit single-ended mode
Avg = 32
Avg = 4
12.8
11.9
12.2
11.4
14.5
13.8
13.9
13.1
鈥�
bits
SINAD
Signal-to-noise
plus distortion
See ENOB
6.02 脳 ENOB + 1.76
dB
THD
Total harmonic
distortion
16-bit differential mode
Avg = 32
16-bit single-ended mode
Avg = 32
鈥�
鈥�94
-85
鈥�
dB
SFDR
Spurious free
dynamic range
16-bit differential mode
Avg = 32
16-bit single-ended mode
Avg = 32
82
78
95
90
鈥�
dB
Table continues on the next page...
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
42
Freescale Semiconductor, Inc.
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