C
參數(shù)資料
型號： PK10N512VLK100
廠商： Freescale Semiconductor
文件頁數(shù)： 38/71頁
文件大小： 0K
描述： IC ARM CORTEX MCU 512K 80-LQFP
產(chǎn)品培訓(xùn)模塊： Kinetis® Cortex-M4 Microcontroller Family
標(biāo)準(zhǔn)包裝： 1
系列： Kinetis
核心處理器： ARM? Cortex?-M4
芯體尺寸： 32-位
速度： 100MHz
連通性： CAN，EBI/EMI，I²C，IrDA，SDHC，SPI，UART/USART
外圍設(shè)備： DMA，I²S，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 56
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 27x16b，D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 80-LQFP
包裝： 托盤
Table 29. 16-bit ADC with PGA operating conditions (continued)
Symbol
Description
Conditions
Min.
Max.
Unit
Notes
Crate
ADC conversion
rate
≤ 13 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
18.484
—
450
Ksps
16 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
37.037
—
250
Ksps
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25s
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4 16-bit ADC with PGA characteristics
Table 30. 16-bit ADC with PGA characteristics
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
IDDA_PGA Supply current
Low power
(ADC_PGA[PGALPb]=0)
—
420
644
μA
IDC_PGA
Input DC current
A
Gain =1, VREFPGA=1.2V,
VCM=0.5V
—
1.54
—
μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
—
0.57
—
μA
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
43
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