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參數(shù)資料
| 型號(hào)： | PIC24FJ128GB110T-I/PF |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 20/22頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | PIC® 24F |
| 核心處理器： | PIC |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，SPI，UART/USART，USB OTG |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 83 |
| 程序存儲(chǔ)器容量： | 128KB（43K x 24） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PIC24FJ128GB110T-I/PFTR |
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2008-2011 Microchip Technology Inc.
DS80369N-page 7
PIC24FJ256GB110 FAMILY
15. Module: UART (IrDA)
When the UARTx is operating in 8-bit mode
(PDSEL<1:0> = 0x) and using the IrDA endec
(IREN = 1), a framing error may occur when
transmitting a data payload of 00h.
Work around:
None.
Affected Silicon Revisions
16. Module: UART (IrDA)
When the UARTx is operating in 9-bit mode
(PDSEL<1:0> = 1x) and using the IrDA endec
(IREN = 1), the module will incorrectly transmit
10 bits when transmitting data payloads of 00h or
80h.
Work around:
None.
Affected Silicon Revisions
17. Module: I2C Module (Master Mode)
Under certain circumstances, a module operating
in Master mode may Acknowledge its own com-
mand addressed to a slave device. This happens
when the following occurs:
10-Bit Addressing mode is used (A10M = 1)
The I2C Master has the same two upper
address bits (I2CADD<9:8>) as the addressed
slave module
In these cases, the Master also Acknowledges the
address command and generates an erroneous I2C
slave interrupt, as well as the I2C master interrupt.
Work around
Several options are available:
When using 10-Bit Addressing mode, make
certain that the master and slave devices do not
share the same 2 MSbs of their addresses.
If this cannot be avoided:
Clear the A10M bit (I2CxCON<10> = 0) prior to
performing a Master mode transmit.
Read the ADD10 bit (I2CxSTAT<8>) to check
for a full 10-bit match whenever a slave I2C
interrupt occurs on the master module.
Affected Silicon Revisions
18. Module: I2C Module (Slave Mode)
Under certain circumstances, a module operating
in Slave mode, may not respond correctly to some
of the special addresses reserved by the I2C
protocol. This happens when the following occurs:
10-Bit Addressing mode is used (A10M = 1)
Bits, A<7:1>, of the slave address
(I2CADD<7:1>) fall into the range of the
reserved 7-bit address ranges: ‘1111xxx’ or
‘0000xxx’.
In these cases, the Slave module Acknowledges
the command and triggers an I2C slave interrupt; it
does not copy the data into the I2CxRCV register
or set the RBF bit.
Work around
Do not set bits, A<7:1>, of the module’s slave
address equal to ‘1111xxx’ or ‘0000xxx’.
Affected Silicon Revisions
A3
A5
A6
X
A3
A5
A6
X
A3
A5
A6
X
A3
A5
A6
X
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