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參數(shù)資料
| 型號： | PIC24FJ128GB110T-I/PF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 2/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | PIC® 24F |
| 核心處理器： | PIC |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，SPI，UART/USART，USB OTG |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 83 |
| 程序存儲器容量： | 128KB（43K x 24） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PIC24FJ128GB110T-I/PFTR |
PIC24FJ256GB110 FAMILY
DS80369N-page 10
2008-2011 Microchip Technology Inc.
28. Module: Oscillator (LPRC)
The LPRC may not automatically restart following
BOR events (i.e., when supply voltage sags to
between the BOR and POR thresholds, then
returns to above the BOR level). When this
happens, systems that use the LPRC clock may
not work. This includes the PLL, Two-Speed
Start-up, Fail-Safe Clock Monitor and the WDT.
Work around
For PLL issues: select a non-PLL Clock mode as
the initial start-up mode, using the FNOSC Config-
uration bits (CW2<10:8>). After the application has
initialized, switch to a PLL Clock mode in software
using the NOSC bits (OSCCON<10:8>). Allow
10
s to elapse between application start-up and a
software clock switch.
For WDT issues: disable the WDT by program-
ming the FWDTEN bit (CW1<7>). After the
application has initialized, enable the WDT in soft-
ware by setting the SWDTEN bit (RCON<5>).
Allow 10
s to elapse between application start-up
and setting SWDTEN.
Affected Silicon Revisions
29. Module: Oscillator (Two-Speed Start-up)
Two-Speed Start-up is not functional. Leaving the
IESO Configuration bit in its default state
(Two-Speed Start-up enabled) may result in
unpredictable operation.
Work around
None. Always program the IESO Configuration bit
to disable the feature (CW2<15> = 0).
Affected Silicon Revisions
30. Module: Output Compare
In PWM mode, the output compare module may
miss a compare event when the current duty cycle
register (OCxRS) value is 0000h (0% duty cycle)
and the OCxRS register is updated with a value of
0001h. The compare event is only missed the first
time a value of 0001h is written to OCxRS and the
PWM output remains low for one PWM period.
Subsequent PWM high and low times occur as
expected.
Work around
If the current OCxRS register value is 0000h, avoid
writing a value of 0001h to OCxRS. Instead, write
a value of 0002h. In this case, however, the duty
cycle will be slightly different from the desired
value.
Affected Silicon Revisions
31. Module: Interrupts (INTx)
Writing to the INTCON2 register may cause an
external interrupt event (inputs on INT0 through
INT4) to be missed. This only happens when the
interrupt event and the write event occur during the
same clock cycle.
Work around
If this cannot be avoided, write the data intended
for INTCON2 to any other register in the interrupt
block of the SFR (addresses, 0080h to 00E0h);
then write the data to INTCON2.
Be certain to write the data to a register not being
actively used by the application, or to any of the
interrupt flag registers, in order to avoid spurious
interrupts. For example, if the interrupts controlled
by IEC5 are not being used in the application, the
code sequence would be:
IEC5 = 0x1E;
INTCON2 = 0x1E;
IEC5 = 0;
It is the user’s responsibility to determine an
appropriate register for the particular application.
Affected Silicon Revisions
A3
A5
A6
X
A3
A5
A6
XX
X
A3
A5
A6
XX
X
A3
A5
A6
XX
X
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