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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F45K80-I/ML
寤犲晢锛� Microchip Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 243/351闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� MCU PIC 32KB FLASH 44QFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� 8-bit PIC® Microcontroller Portfolio
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 45
绯诲垪锛� PIC® XLP™ 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 64MHz
閫ｉ€氭€э細 ECAN锛孖²C锛孡IN锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孡VD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 35
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 32KB锛�16K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 1K x 8
RAM 瀹归噺锛� 3.6K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 11x12b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 44-VQFN 瑁搁湶鐒婄洡
鍖呰锛� 绠′欢
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2010-2012 Microchip Technology Inc.
DS39977F-page 317
PIC18F66K80 FAMILY
21.4.6.1
I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic 鈥�0鈥�. Serial data is
transmitted, 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic 鈥�1鈥�. Thus, the first byte transmitted is a 7-bit slave
address, followed by a 鈥�1鈥� to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received, 8 bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
The Baud Rate Generator, used for the SPI mode
operation, is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
for more details.
A typical transmit sequence would go as follows:
1.
The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
2.
SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3.
The user loads the SSPBUF with the slave
address to transmit.
4.
Address is shifted out the SDA pin until all 8 bits
are transmitted.
5.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6.
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7.
The user loads the SSPBUF with eight bits of
data.
8.
Data is shifted out the SDA pin until all 8 bits are
transmitted.
9.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
鐩搁棞(gu膩n)PDF璩囨枡
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PIC18F45K80T-I/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB FL 4KBRM 16MIPS 12bit ADC CTMU RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F4610-E/ML 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 3968 RAM 36 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F4610-E/P 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 3968 RAM 36 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F4610-E/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 64KB 3968 RAM 36 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
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*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣(g貌u)

鎴戠殑鑱�(li谩n)绯绘柟寮�

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    • 閲囪喘
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    • 浼氬憳