參數(shù)資料
型號: PIC18F45J50-I/PT
廠商: Microchip Technology
文件頁數(shù): 146/164頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32K 2V 44-TQFP
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 160
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
PIC18F46J50 FAMILY
DS39931D-page 82
2011 Microchip Technology Inc.
6.2
PIC18 Instruction Cycle
6.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the PC is incremented
on every Q1; the instruction is fetched from the pro-
gram memory and latched into the Instruction Register
(IR) during Q4. The instruction is decoded and exe-
cuted during the following Q1 through Q4. Figure 6-4
illustrates the clocks and instruction execution flow.
6.2.2
INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the PC to change (e.g., GOTO), then
two cycles are required to complete the instruction
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the IR in the Q1 cycle. This instruction is then
decoded and executed during the Q2, Q3 and Q4
cycles. Data memory is read during Q2 (operand read)
and written during Q4 (destination write).
FIGURE 6-4:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 6-3:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC
PC + 2
PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
Note:
All instructions are single-cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then exe-
cuted.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h
Fetch 1
Execute 1
2. MOVWF LATB
Fetch 2
Execute 2
3. BRA SUB_1
Fetch 3
Execute 3
4. BSF
LATA, 3 (Forced NOP)
Fetch 4
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
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