參數(shù)資料
型號: PIC18F45J50-I/PT
廠商: Microchip Technology
文件頁數(shù): 130/164頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32K 2V 44-TQFP
產(chǎn)品培訓模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標準包裝: 160
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
PIC18F46J50 FAMILY
DS39931D-page 68
2011 Microchip Technology Inc.
5.7
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TO, PD, POR and BOR) are set or cleared differently in
different Reset situations, as indicated in Table 5-1.
These bits are used in software to determine the nature
of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
POR and BOR, MCLR and WDT Resets and WDT
wake-ups.
TABLE 5-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter(1)
RCON Register
STKPTR Register
CM
RI
TO
PD
POR
BOR
STKFUL STKUNF
Power-on Reset
0000h
111100
0
RESET
instruction
0000h
u0uuuu
u
Brown-out Reset
0000h
1111u0
u
Configuration Mismatch Reset
0000h
0uuuuu
u
MCLR Reset during
power-managed Run modes
0000h
uu1uuu
u
MCLR Reset during
power-managed Idle modes and
Sleep mode
0000h
uu10uu
u
MCLR Reset during full-power
execution
0000h
uuuuuu
u
Stack Full Reset (STVREN = 1)
0000h
uuuuuu
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
uuuuuu
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
uuuuuu
u
1
WDT time-out during full-power
or power-managed Run modes
0000h
uu0uuu
u
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
uu00uu
u
Interrupt exit from
power-managed modes
PC + 2
uuu0uu
u
Legend: u
= unchanged
Note 1:
When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
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