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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC18F45J11-I/ML |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 29/228闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 32K 2V 44-QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | XLP Deep Sleep Mode PIC18 J Series MCU Overview 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 45 |
| 绯诲垪锛� | PIC® XLP™ 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 48MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 34 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 32KB锛�16K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 3.8K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.15 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 13x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 44-VQFN 瑁搁湶鐒婄洡(p谩n) |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 657 (CN2011-ZH PDF) |
| 閰嶇敤锛� | AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN |
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dsPIC30F3014/4013
DS70138G-page 124
2010 Microchip Technology Inc.
size and Frame Sync generator control bits. A new I2S
data transfer boundary is marked by a high-to-low or a
low-to-high transition edge on the COFS pin.
18.3.6
SLAVE FRAME SYNC OPERATION
When the DCI module is operating as a Frame Sync
slave (COFSD = 1), data transfers are controlled by the
Codec device attached to the DCI module. The
COFSM control bits control how the DCI module
responds to incoming COFS signals.
In the Multichannel mode, a new data frame transfer
begins one CSCK cycle after the COFS pin is sampled
high (see Figure 18-2). The pulse on the COFS pin
resets the Frame Sync generator logic.
In the I2S mode, a new data word is transferred one
CSCK cycle after a low-to-high or a high-to-low transi-
tion is sampled on the COFS pin. A rising or falling
edge on the COFS pin resets the Frame Sync
generator logic.
In the AC-Link mode, the tag slot and subsequent data
slots for the next frame is transferred one CSCK cycle
after the COFS pin is sampled high.
The COFSG and WS bits must be configured to
provide the proper frame length when the module is
operating in the Slave mode. Once a valid Frame Sync
pulse has been sampled by the module on the COFS
pin, an entire data frame transfer takes place. The
module will not respond to further Frame Sync pulses
until the data frame transfer has completed.
FIGURE 18-2:
FRAME SYNC TIMING, MULTICHANNEL MODE
FIGURE 18-3:
FRAME SYNC TIMING, AC-LINK START-OF-FRAME
FIGURE 18-4:
I2S INTERFACE FRAME SYNC TIMING
CSCK
CSDI/CSDO
COFS
MSB
LSB
Tag
MSb
BIT_CLK
CSDO or CSDI
SYNC
Tag
bit 14
S12
LSb
S12
bit 1
S12
bit 2
Tag
bit 13
MSB
LSB MSB
LSB
CSCK
CSDI or CSDO
WS
Note:
A 5-bit transfer is shown here for illustration purposes. The I2S protocol does not specify word length 鈥� this
will be system dependent.
鐩搁棞(gu膩n)PDF璩囨枡 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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