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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC18F45J11-I/ML |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 225/228闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 32K 2V 44-QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | XLP Deep Sleep Mode PIC18 J Series MCU Overview 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 45 |
| 绯诲垪锛� | PIC® XLP™ 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 48MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 34 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 32KB锛�16K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 3.8K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.15 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 13x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 44-VQFN 瑁搁湶鐒婄洡(p谩n) |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 657 (CN2011-ZH PDF) |
| 閰嶇敤锛� | AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN |
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dsPIC30F3014/4013
DS70138G-page 96
2010 Microchip Technology Inc.
14.12.2
I2C MASTER RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (I2CCON<3>). The I2C
module must be Idle before the RCEN bit is set; other-
wise, the RCEN bit is disregarded. The Baud Rate
Generator begins counting and on each rollover, the
state of the SCL pin ACK and data are shifted into the
I2CRSR on the rising edge of each clock.
14.12.3
BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to 鈥�0鈥� and
stops until another reload has taken place. If clock
arbitration is taking place, for instance, the BRG is
reloaded when the SCL pin is sampled high.
As per the I2C standard, FSCK may be 100 kHz or
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of 鈥�0鈥� or 鈥�1鈥� are illegal.
EQUATION 14-1:
SERIAL CLOCK RATE
14.12.4
CLOCK ARBITRATION
Clock arbitration occurs when the master deasserts the
SCL pin (SCL allowed to float high) during any receive,
transmit, or Restart/Stop condition. When the SCL pin
is allowed to float high, the Baud Rate Generator
(BRG) is suspended from counting until the SCL pin is
actually sampled high. When the SCL pin is sampled
high, the Baud Rate Generator is reloaded with the
contents of I2CBRG and begins counting. This ensures
that the SCL high time is always at least one BRG roll-
over count in the event that the clock is held low by an
external device.
14.12.5
MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-master operation support is achieved by bus arbi-
tration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a 鈥�1鈥� on SDA by letting SDA float high
while another master asserts a 鈥�0鈥�. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a 鈥�1鈥� and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master sets the MI2CIF pulse and resetS the master
portion of the I2C port to its Idle state.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are deasserted and a
value can now be written to I2CTRN. When the user
services the I2C master event Interrupt Service
Routine, if the I2C bus is free (i.e., the P bit is set), the
user can resume communication by asserting a Start
condition.
If a Start, Restart, Stop or Acknowledge condition was
in progress when the bus collision occurred, the condi-
tion is aborted, the SDA and SCL lines are deasserted
and the respective control bits in the I2CCON register
are cleared to 鈥�0鈥�. When the user services the bus
collision Interrupt Service Routine, and if the I2C bus is
free, the user can resume communication by asserting
a Start condition.
The master continues to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit is
set.
A write to the I2CTRN starts the transmission of data at
the first data bit, regardless of where the transmitter left
off when bus collision occurred.
In a multi-master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
14.13 I2C Module Operation During CPU
Sleep and Idle Modes
14.13.1
I2C OPERATION DURING CPU
SLEEP MODE
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic 鈥�0鈥�. If
Sleep occurs in the middle of a transmission and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
14.13.2
I2C OPERATION DURING CPU IDLE
MODE
For the I2C, the I2CSIDL bit determines if the module
stops or continues on Idle. If I2CSIDL = 0, the module
continues operation on assertion of the Idle mode. If
I2CSIDL = 1, the module stops on Idle.
I2CBRG =
FCY
FSCK
1,111,111
鈥� 1
鈥�
()
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