WAKE-UP FROM SLEEP THROUGH INTERRUPT
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F4585-I/PT
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PIC18FXX39
DS30485A-page 206
Preliminary
2002 Microchip Technology Inc.
FIGURE 20-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
20.4
Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 FLASH devices differs significantly from other
PICmicro devices. The user program memory is
divided on binary boundaries into individual blocks,
each of which has three separate code protection bits
associated with it:
Code Protect bit (CPn)
Write Protect bit (WRTn)
External Block Table Read bit (EBTRn)
The code protection bits are located in Configuration
Registers 5L through 7H. Their locations within the
registers are summarized in Table 20-3.
In the PIC18FXX39 family, program memory is divided
into segments of 8 Kbytes. The first block in turn
divided into a boot block of 512 bytes and a separately
protected remainder (Block 0) of 7.5 Kbytes. This
means for PIC18FXX39 devices, that there may be up
to five blocks, depending on the program memory size.
The organization of the blocks and their associated
code protection bits are shown in Figure 20-3.
For PIC18FX439 devices, program memory is divided
into three blocks: a boot block, Block 0 (7.5 Kbytes)
and Block 1 (8 Kbytes). Block 1 is further divided in
half; the upper portion above 3000h is reserved, and
unavailable to user applications. The entire block can
be protected as a whole by bits CP1, WRT1 and
EBTR1. By default, Block 1 is not code protected.
For PIC18FX539 devices, program memory is divided
into five blocks: the boot block, Block 0 (7.5 Kbytes),
and Blocks 1 through 3 (8 Kbytes). Code protection is
implemented for the boot block and Blocks 0 through 2.
There is no provision for code protection for Block 3.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO(4)
INT pin
INTF Flag
(INTCON<1>)
GIEH bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC
PC+2
PC+4
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 2)
SLEEP
Processor in
SLEEP
Interrupt Latency(3)
Inst(PC + 4)
Inst(PC + 2)
Inst(0008h)
Inst(000Ah)
Inst(0008h)
Dummy Cycle
PC + 4
0008h
000Ah
Dummy Cycle
TOST(2)
PC+4
Note
1:
XT, HS or LP Oscillator mode assumed.
2:
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
3:
TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Osc modes.
4:
CLKO is not available in these Osc modes, but shown here for timing reference.
Note:
The reserved segments of the program
memory space are used by the Motor Con-
trol kernel. For the kernel to function prop-
erly, this area must not be write protected.
If users are developing applications that
require code protection for PIC18FX439
devices, they should restrict program code
(or at least those sections requiring protec-
tion) to below the 1FFFh memory
boundary.
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