[ label ] BTFSC f,b[,a] Ope" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F4539T-I/ML
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 142/322闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU FLASH 12KX16 EE A/D 44QFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,600
绯诲垪锛� PIC® 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 40MHz
閫i€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣嶏紝LVD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 24KB锛�12K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶у皬锛� 256 x 8
RAM 瀹归噺锛� 1408 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.2 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 44-VQFN 瑁搁湶鐒婄洡
鍖呰锛� 甯跺嵎 (TR)
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PIC18FXX39
DS30485A-page 224
Preliminary
2002 Microchip Technology Inc.
BTFSC
Bit Test File, Skip if Clear
Syntax:
[ label ] BTFSC f,b[,a]
Operands:
0
鈮� f 鈮� 255
0
鈮� b 鈮� 7
a
鈭� [0,1]
Operation:
skip if (f<b>) = 0
Status Affected:
None
Encoding:
1011
bbba
ffff
Description:
If bit 'b' in register 鈥檉' is 0, then the
next instruction is skipped.
If bit 'b' is 0, then the next instruction
fetched during the current instruction
execution is discarded, and a NOP is
executed instead, making this a two-
cycle instruction. If 鈥榓(ch菐n)鈥� is 0, the
Access Bank will be selected, over-
riding the BSR value. If 鈥榓(ch菐n)鈥� = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
FLAG, 1, 0
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
=
0;
PC
=
address (TRUE)
If FLAG<1>
=
1;
PC
=
address (FALSE)
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0
鈮� f 鈮� 255
0
鈮� b 鈮� 7
a
鈭� [0,1]
Operation:
skip if (f<b>) = 1
Status Affected:
None
Encoding:
1010
bbba
ffff
Description:
If bit 'b' in register 'f' is 1, then the
next instruction is skipped.
If bit 'b' is 1, then the next instruction
fetched during the current instruc-
tion execution, is discarded and a
NOP
is executed instead, making this
a two-cycle instruction. If 鈥榓(ch菐n)鈥� is 0, the
Access Bank will be selected, over-
riding the BSR value. If 鈥榓(ch菐n)鈥� = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSS
:
FLAG, 1, 0
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
=
0;
PC
=
address (FALSE)
If FLAG<1>
=
1;
PC
=
address (TRUE)
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
PIC18F4550EPT 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:
PIC18F4550-I/ML 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32kBF 2048RM FSUSB2 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F4550-I/P 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32kBF 2048RM FSUSB2 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F4550-I/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32kBF 2048RM FSUSB2 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F4550T-I/ML 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32kBF 2048RM FSUSB2 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT