2002 Microchip Technology Inc.
Preliminary
DS30485A-page 175
PIC18FXX39
FIGURE 17-5:
ASYNCHRONOUS RECEPTION
TABLE 17-7:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
START
bit
bit7/8
bit1
bit0
bit7/8
bit0
STOP
bit
START
bit
START
bit
bit7/8 STOP
bit
RX (pin)
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
STOP
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing
the OERR (overrun) bit to be set.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
RESETS
INTCON
GIE/GIEH PEIE/
GIEL
TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
0000 000x
0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
—
TMR2IF TMR1IF 0000 0000
0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
—
TMR2IE TMR1IE 0000 0000
0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
—
TMR2IP TMR1IP 0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RX9D
0000 -00x
RCREG
USART Receive Register
0000 0000
TXSTA
CSRC
TX9
TXEN
SYNC
—BRGH
TRMT
TX9D
0000 -010
SPBRG
Baud Rate Generator Register
0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits
clear.
