TABLE 23-16: I2" />
鍙冩暩璩囨枡
鍨嬭櫉锛� PIC18F4539T-E/ML
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩锛� 205/322闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC PIC MCU FLASH 12KX16 44QFN
妯欐簴鍖呰锛� 1,600
绯诲垪锛� PIC® 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 40MHz
閫i€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷倷锛� 娆犲妾㈡脯/寰╀綅锛孡VD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁革細 32
绋嬪簭瀛樺劜鍣ㄥ閲忥細 24KB锛�12K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 256 x 8
RAM 瀹归噺锛� 1408 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.2 V ~ 5.5 V
鏁告摎杞夋彌鍣細 A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏ч儴
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 44-VQFN 瑁搁湶鐒婄洡
鍖呰锛� 甯跺嵎 (TR)
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�绗�173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�绗�179闋�绗�180闋�绗�181闋�绗�182闋�绗�183闋�绗�184闋�绗�185闋�绗�186闋�绗�187闋�绗�188闋�绗�189闋�绗�190闋�绗�191闋�绗�192闋�绗�193闋�绗�194闋�绗�195闋�绗�196闋�绗�197闋�绗�198闋�绗�199闋�绗�200闋�绗�201闋�绗�202闋�绗�203闋�绗�204闋�鐣跺墠绗�205闋�绗�206闋�绗�207闋�绗�208闋�绗�209闋�绗�210闋�绗�211闋�绗�212闋�绗�213闋�绗�214闋�绗�215闋�绗�216闋�绗�217闋�绗�218闋�绗�219闋�绗�220闋�绗�221闋�绗�222闋�绗�223闋�绗�224闋�绗�225闋�绗�226闋�绗�227闋�绗�228闋�绗�229闋�绗�230闋�绗�231闋�绗�232闋�绗�233闋�绗�234闋�绗�235闋�绗�236闋�绗�237闋�绗�238闋�绗�239闋�绗�240闋�绗�241闋�绗�242闋�绗�243闋�绗�244闋�绗�245闋�绗�246闋�绗�247闋�绗�248闋�绗�249闋�绗�250闋�绗�251闋�绗�252闋�绗�253闋�绗�254闋�绗�255闋�绗�256闋�绗�257闋�绗�258闋�绗�259闋�绗�260闋�绗�261闋�绗�262闋�绗�263闋�绗�264闋�绗�265闋�绗�266闋�绗�267闋�绗�268闋�绗�269闋�绗�270闋�绗�271闋�绗�272闋�绗�273闋�绗�274闋�绗�275闋�绗�276闋�绗�277闋�绗�278闋�绗�279闋�绗�280闋�绗�281闋�绗�282闋�绗�283闋�绗�284闋�绗�285闋�绗�286闋�绗�287闋�绗�288闋�绗�289闋�绗�290闋�绗�291闋�绗�292闋�绗�293闋�绗�294闋�绗�295闋�绗�296闋�绗�297闋�绗�298闋�绗�299闋�绗�300闋�绗�301闋�绗�302闋�绗�303闋�绗�304闋�绗�305闋�绗�306闋�绗�307闋�绗�308闋�绗�309闋�绗�310闋�绗�311闋�绗�312闋�绗�313闋�绗�314闋�绗�315闋�绗�316闋�绗�317闋�绗�318闋�绗�319闋�绗�320闋�绗�321闋�绗�322闋�
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 281
PIC18FXX39
TABLE 23-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4.0
鈥�
s
PIC18FXXX must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
鈥�
s
PIC18FXXX must operate at a
minimum of 10 MHz
SSP Module
1.5 TCY
鈥�
101
TLOW
Clock low time
100 kHz mode
4.7
鈥�
s
PIC18FXXX must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
鈥�
s
PIC18FXXX must operate at a
minimum of 10 MHz
SSP Module
1.5 TCY
鈥�
102
TR
SDA and SCL rise
time
100 kHz mode
鈥�
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
CB is specified to be from
10 to 400 pF
103
TF
SDA and SCL fall
time
100 kHz mode
鈥�
1000
ns
VDD
鈮� 4.2V
400 kHz mode
20 + 0.1 CB
300
ns
VDD
鈮� 4.2V
90
TSU:STA
START condition
setup time
100 kHz mode
4.7
鈥�
s
Only relevant for Repeated
START condition
400 kHz mode
0.6
鈥�
s
91
THD:STA
START condition hold
time
100 kHz mode
4.0
鈥�
s
After this period, the first clock
pulse is generated
400 kHz mode
0.6
鈥�
s
106
THD:DAT
Data input hold time
100 kHz mode
0
鈥�
ns
400 kHz mode
0
0.9
s
107
TSU:DAT
Data input setup time 100 kHz mode
250
鈥�
ns
(Note 2)
400 kHz mode
100
鈥�
ns
92
TSU:STO
STOP condition
setup time
100 kHz mode
4.7
鈥�
s
400 kHz mode
0.6
鈥�
s
109
TAA
Output valid from
clock
100 kHz mode
鈥�
3500
ns
(Note 1)
400 kHz mode
鈥�
ns
110
TBUF
Bus free time
100 kHz mode
4.7
鈥�
s
Time the bus must be free
before a new transmission can
start
400 kHz mode
1.3
鈥�
s
D102
CB
Bus capacitive loading
鈥�
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement TSU:DAT
鈮� 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
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PIC18F4550EPT 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:
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