
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 79
PIC18FXX39
REGISTER 8-9:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0
R/W-1
U-1
—
EEIP(1)
BCLIP(1)
LVDIP(1) TMR3IP(1)
—
bit 7
bit 0
bit 7-5
Unimplemented: Read as '0'
bit 4
EEIP(1): Data EEPROM/FLASH Write Operation Interrupt Priority bit
1
= High priority
0
= Low priority
bit 3
BCLIP(1): Bus Collision Interrupt Priority bit
1
= High priority
0
= Low priority
bit 2
LVDIP(1): Low Voltage Detect Interrupt Priority bit
1
= High priority
0
= Low priority
bit 1
TMR3IP(1): TMR3 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
bit 0
Unimplemented: Read as ‘1’
Note 1: Maintain this bit cleared (= 0).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown